I'm trying to measure the duration of a non periodic signal(message) on FPGA, as below : signal

I want to measure the duration of the measured signal by counting the number of reference clock's period. I set the first rising edge as the start trigger, but how should set the stop trigger?

I have no idea how to do this, can you give me some advice? I want to implement this on FPGA with VHDL.

  • \$\begingroup\$ You are doing it backwards. Instead have a process triggered by the ref clock, and check the signal level within this process. \$\endgroup\$ – Eugene Sh. Feb 2 '18 at 18:11
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    \$\begingroup\$ You'd have to identify the message protocol in enough detail to uniquely identify the start and end transitions. Otherwise, you just have a series of transitions that don't convey any meaning at all. If it's just a matter of "timeout" (no transitions for a given period of time), then you'll have to remember the count for the most recent transition, and use that once the timeout occurs. \$\endgroup\$ – Dave Tweed Feb 2 '18 at 18:13
  • \$\begingroup\$ If your picture is more or less accurate: You need a much higher sampling clock as at the moment the signal and clock have the same min high/low period. Look up Nyquist. \$\endgroup\$ – Oldfart Feb 2 '18 at 18:33


  • A "message" is a collection of transitions, with some sizable gap between messages that contains no transitions.
  • The clock period is smaller than the shortest gap between signal transitions.

Here's a block diagram; I'll leave it to you to convert it to your favorite HDL.


simulate this circuit – Schematic created using CircuitLab

  • U1 is a two (or more) stage synchronizer that makes sure the input signal is synchronous to the clock.
  • U2 is a synchronous edge detector that outputs a 1-clock pulse for every edge at the output of U1.
  • U3 is the "timeout" counter. It gets reset on every edge, and the message is over when it overflows.
  • U4 is a simple set-reset FF that keeps track of whether we're "in a message" (output is low) or "between messages" (output is high). It gets set when U3 overflows, and cleared whenever U2 detects an edge.
  • U5 is the "duration" counter. It needs to have enough bits to count the duration of the longest message. It starts counting on the first edge detected, and keeps counting until U3 overflows.
  • U6 is a simple N-bit register that captures the value of U5 for each detected edge. When U3 overflows, it contains the count for the last edge that occurred in the message.

Each of these blocks is just a couple of lines of code in either VHDL or Verilog.

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  • \$\begingroup\$ Thanks so much for your detailed and clear answer. This looks great! I learned a lot from your answer. Thanks again! \$\endgroup\$ – Joe Feb 3 '18 at 2:23

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