# Synthesis Result : RTL vs Technology Map Viewer

I am evaluating this code below. But I saw that the logic output of the RTL and Technology Map Viewer are different. I use Quartus Prime Elite Edition. Am I missing something?

this is the truth table

                      RTL                          Technology Map
A    (NOT A)   p_a    ((A XOR p_a) AND A)          ((NOT A) AND p_a)
0      1        0           0                            0
0      1        1           0                            1
1      0        0           1                            0
1      0        1           0                            0


library ieee;
use ieee.std_logic_1164.all;

port (
clk             : in std_logic;
rst             : in std_logic;
a               : in std_logic;
b               : in std_logic;
c               : in std_logic;
d               : in std_logic;
e               : in std_logic;
keypad      : out std_logic_vector (4 downto 0)
);

signal p_a, p_b, p_c, p_d, p_e  : std_logic;

BEGIN

KEY:    process(A, B, C, D, E, rst, clk)
begin
if      rst = '1' then
p_a <= '0';
p_b <= '0';
p_c <= '0';
p_d <= '0';
p_e <= '0';
elsif clk'event AND clk='1' then
p_a <= A;
p_b <= B;
p_c <= C;
p_d <= D;
p_e <= E;
end if;
end process;

keypad(4) <= '1' when a /= p_a and a = '1' else '0';
keypad(3) <= (B XOR p_b) AND B;
END architecture;


I appreciate any suggestion.

You'll find this a lot when using the graphical netlist viewers. The compiler does clever things you may not expect, and which aren't always immediately obvious.

The reason is because the combinational logic cell has inverting inputs in your example. You need to check both the contents (F) and the comb cell itself in the properties view:

Then the contents:

The comb cell:

There are your missing inverters. The combinational cell as "Active Low" inputs, so the internal logic has to invert them.

You can look at the equation view to confirm:

Here we see the equation becomes:

$$\overline{p\_a} \cdot a$$

• Hi, thank you. I see it now. just another doubt. in Technology Map, there are two bubbles, one for port A and one for port B. but, why the equation is only written as: <c> keypad~1 = !DATAA & DATAB while in F tab is makes more sense. there is only one bubble in the post B and the equation is: <c> F = DATAA & !DATAB – Codelearner777 Feb 3 '18 at 12:04
• @Codelearner777 the F tab equation is telling you what is inside the LUT. The keypad~1 tab is describing the LUT itself. – Tom Carpenter Feb 3 '18 at 12:36
• Take the F = DATAA & !DATAB, then invert both inputs because the LUT has active low inputs (see the Ports tab). Your equation then becomes F = !DATAA & !!DATAB = !DATAA & DATAB – Tom Carpenter Feb 3 '18 at 12:38
• Thank you again. Everything is clear now. This is my first time using Synthesis CAD Tool. I already picked your answer as the answer. – Codelearner777 Feb 3 '18 at 14:01
• @Codelearner777 If you are happy that it answers your question, you can upvote and accept it. – Tom Carpenter Feb 3 '18 at 14:25

They are equivalent. The code/rtl-viewer give the equation as (B xor p_b) and B and the technology map view shows it as B and !p_b. The former can be simplified to the latter as follows

$(A \oplus B)A$

$(A\bar{B} + \bar{A}B)B$

$AA\bar{B} + A\bar{A}B$

$A\bar{B} + 0$ ($A\bar{A}$ is 0, so the right side is 0)

$A\bar{B}$

• the technology map view shows it as (!B AND p_b). – Codelearner777 Feb 2 '18 at 23:18
• Hmm. Try seeing if a~input contains an inverter – C_Elegans Feb 2 '18 at 23:27
• yeah, that is the only possibility. but I cannot find the documentation so far. I will look for it again tomorrow. thanks anyway. – Codelearner777 Feb 3 '18 at 0:00

Both are equivalent. RTL viewer shows what digital logic is implemented by your HDL code. It would be what you draw on a paper, if you were to design a digital circuit that satisfy your functional requirement. Technology viewer shows how this digital circuit is implemented inside FPGA. It depends on the technology inside FPGA. For eg. An OR gate is implemented as a simple LTU inside FPGA. It shows how LUTs are used , which IOBs it has used, whether it is using buffers on lines, etc.

In your technology viewer, it shows that the combination logic produced by two logic gates is implemented as a single truth table in an LUT inside FPGA. Just as C_elegants has answered.

The Logic mapper uses "functional" symbols, which is just a square with what function that block fulfills. This can map onto all kinds of logic.

For example if you use a '+' the function will be 'adder': a square with two inputs and an output. Which maps on a numerous gates. It can also be mapped on different gates e.g. a slow ripple carry adder or a faster carry-look ahead adder.

I also allows a tool to work with a mixture of e.g. Verilog and VHDL. They use two compilers to map the language on functional primitives and then they can use one tool to go to gates and optimize.

And they can use a different tool to go to gates and optimize for a totally different FPGA type.

• if we see the properties of the logic_cell_comb, we can see the exact circuit or its logic equation. – Codelearner777 Feb 2 '18 at 23:17
• I don't know. I have used Xilinx and Synopsys for ASICs. All these tools work in the same way. I never have had the urge to look inside them. – Oldfart Feb 2 '18 at 23:22