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I'm currently building my very own processor using discrete logic (74LSxx series and that) using my very own instruction set architecture. I am starting to rack up a bit of a bill because all the chips I need. For any of you that have seen people build homebrew CPUs like this, no one that I have read about has used an SRAM chip as their register file

Would it be considered cheating if I used an SRAM chip as opposed to a TON of '374 flip flop chips for the registers? This is supposed to be a processor made from discrete chips

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closed as primarily opinion-based by Chris Stratton, Harry Svensson, RoyC, Chupacabras, Dave Tweed Feb 4 '18 at 12:50

Many good questions generate some degree of opinion based on expert experience, but answers to this question will tend to be almost entirely based on opinions, rather than facts, references, or specific expertise. If this question can be reworded to fit the rules in the help center, please edit the question.

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    \$\begingroup\$ Cheating? By whose rules? \$\endgroup\$ – Marla Feb 3 '18 at 16:47
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    \$\begingroup\$ I don't know if it's cheating, but it's going to make your design slower if it can only access 1 register at a time. \$\endgroup\$ – The Photon Feb 3 '18 at 16:48
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    \$\begingroup\$ Yeah, some professor will tell the authorities about it. \$\endgroup\$ – Harry Svensson Feb 3 '18 at 16:56
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    \$\begingroup\$ @GregoryKornblum "Mary, I've been unfaithful to you... I've cheated on you with an SRAM chip, it began with a soldering iron, one thing led to another and we both ended up on the PCB" \$\endgroup\$ – Harry Svensson Feb 3 '18 at 18:40
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    \$\begingroup\$ If it's cheating you're in good company en.wikipedia.org/wiki/Texas_Instruments_TMS9900 \$\endgroup\$ – Bruce Abbott Feb 3 '18 at 20:05
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No, it is not cheating around any rules. This is because there aren't any rules in the first place.

This is your project. You define it. You can implement it in any way that satisfies you. Nobody else cares.

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    \$\begingroup\$ Note this means it is cheating if you want it to be cheating. \$\endgroup\$ – immibis Feb 3 '18 at 23:25
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As asked, this is purely a matter of opinion, hence not a valid question here.

However do note that conventional processors require 3 port access to the register file - two to obtain operands, one to write back the result. So you'll need substantially more complex datapath and control circuitry to prefetch and cache operands if you want to use a single port RAM. Or you can build something with a distinct and more privileged accumulator, and an instruction set only permitting a single non-accumulator register to appear as a source or destination (for that matter, there are CPUs with only an accumulator)

Using two memories written in parallel and read individually could simplify things a little, but that trick works best with dual port memories. Those are something you can buy in IC form, as well as being the common form of FPGA block RAMs.

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  • \$\begingroup\$ I'll note that 3-port (or even 2-port) register arrays were a relatively late innovation. It was something we attempted when I was first in the biz ca 1973, but the expense was too great for most designs with more than 4 registers. \$\endgroup\$ – Hot Licks Feb 4 '18 at 1:34
  • \$\begingroup\$ You could just use two SRAM chips in parallel, one for each operand and write to both. \$\endgroup\$ – Michael Feb 4 '18 at 6:56
  • \$\begingroup\$ @Michael - note above "Using two memories written in parallel and read individually..." but if they are single port models some muxing logic will be needed to toggle the address lines between distinct reads and shared writes to the address of the result register during appropriate cycles. \$\endgroup\$ – Chris Stratton Feb 4 '18 at 7:39
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Your project, your rules.

But as they say, "perfect is the enemy of done". If the project seems to be getting out of hand (be it with regard to complexity, time required, or money required), cutting yourself some slack on one corner of the design may be the difference between a nifty (if a bit insane) accomplishment, and a project that never got finished.

Besides, even if you do decide to "cheat", there's always the option of making version 2 later, with less shortcuts. You could even try to take a possible future "upgrade" into account in the first version of the design, if you want to spend some time to make the "upgrade" easier.

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Yes! It is even cheating if you use any components you haven't made yourself solely from the natural materials you can find in your own garden.

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  • \$\begingroup\$ But then you'd be cheating if you steal sand from golf course bunkers to make silicon. I'm assuming this answer is trying to help the OP question what is truly considered "cheating". \$\endgroup\$ – Alan Campbell Feb 3 '18 at 23:58
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    \$\begingroup\$ Yes, and the energy for this process must come from the sun, wind, or trees you have planted yourself, all from within the garden. No cheating is allowed using electricity from the grid or getting fossil fuels from elsewhere. \$\endgroup\$ – Peter Mortensen Feb 4 '18 at 0:07
  • \$\begingroup\$ Indeed. The correct way to start is to bang a quartz rock and some anthracite together until it forms silicon. It may happen in appreciable quantities before the Universe goes belly up. \$\endgroup\$ – Stian Yttervik Feb 4 '18 at 1:08
  • \$\begingroup\$ Darn! So I can't use frac sand? \$\endgroup\$ – Hot Licks Feb 4 '18 at 1:34
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People who make homebrew CPUs (have you looked at any?) tend to use SRAM for registers. Nobody in their right mind would solder up a load of flip-flops. Never mind affording it, the power needs, and the chances of getting it wired up properly.

You don't need dual-ported if you only ever do one read or write at a time. So to, eg, INC a register, have your CPU read it on one cycle, into a buffer. Increment the buffer in the next cycle, then write it back in a third. Time-multiplexing!

Some sort of buffering will be needed if you're feeding 2 registers' contents into a ALU. You could perhaps use just one buffer and get the second operand "live" from the SRAM. But of course there's no "increment" pin on an SRAM chip! You'll figure out where the buffering needs to be.

That said, there are 74-series registers. Originally entire CPUs were made of 74-series, or at least discrete logic chips, before the 74 series was invented. Searching "74 series register file" gave a few leads. Though of course just because it was made once doesn't mean you'll find it now.

Have you looked into FPGAs, or even CPLDs and PALs? PALs are too small to do a CPU with, but a few of them mixed in with the other logic might save you a few chips. In an FPGA though you could implement entire CPUs. FPGAs are basically thousands of logic gates on a chip. You can choose what logic each gate does, and how they are connected. You do this by writing code, like software. Then shoot the results down a USB lead to a programmer.

FPGAs are used a lot in consumer goods, and in many many other fields.

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  • \$\begingroup\$ I can't believe how desparate I was using D FF registers to make a PIO UART and all in 883B chips in 1977. \$\endgroup\$ – Sunnyskyguy EE75 Feb 4 '18 at 7:46
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    \$\begingroup\$ That's the slippery slope. You go from discrete components, to a memory chip, to a CPLD, to an FPGA, then you realize the FPGA has a CPU hard core built in, and next thing you know all you did was solder an FPGA and some passive components to a PCB and it's no fun at all. \$\endgroup\$ – fluffysheap Feb 4 '18 at 9:13
  • \$\begingroup\$ @fluffysheap, and what is so fun of soldering a big bunch of DIP chips? And then have no Logic Analyzer to see signals? And then fight power glitches forever? This all sounds like a college project, with a professor who is stuck in 70-s/80-s. I have seen one "microprocessor design" class where all was revolving around i8237 DMA chip, with bus access made of discrete gates, on paper. A suggestion to build all thing using FPGA/Verilog tools with full timing analysis and all timing diagrams was rejected. FPGA is a sure way to learn processors. And gives a very practical skill as well. \$\endgroup\$ – Ale..chenski Feb 7 '18 at 7:29
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I am also aware of a processor that uses single ported SRAM for the general-purpose register file, a very fast/efficient processor in fact.

Where do you think the term register file comes from? Registers in an SRAM.

With a pipelined architecture you could have a single port SRAM and not necessarily have a performance hit. A single ported SRAM implementation would make sense for having a lot of registers, say 128, 256, or 512 general-purpose registers.

Yes, it is perfectly fine to implement your "registers" in a register file built from an SRAM, so long as your design works.

I am not sure if you are trying to implement an existing processor/instruction set or make your own. In either case, doing it with discrete 74xx parts, performance is not necessarily a goal compared to sanity and success. If you have some SRAMs from that generation then absolutely. You can tie LEDs to the address and data bus to make (more) blinky lights showing signs of life.

Or you can take the 6502 approach, and have 256 virtual or indirect registers (page zero) that are just memory or perhaps special memory. And your real general-purpose register (or general-purpose registers) are few and fit in a few parts. It worked quite well for MOS Technology. (The architecture, not necessarily the implementation, although they have shaved and scanned and reverse engineered the 6502 so you can see how they actually did implement it).

You probably also want to "cheat" and use a ROM for the look up table that implements your microcode...Even though that isn't cheating either; it is a known solution.

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  • \$\begingroup\$ "With a pipelined architecture you could have a single port sram and not necessarily have a performance hit" - not really. Such a bottleneck means that you get a pipeline stall on any series of register operations, even independent ones. If you cannot for a sequence of instructions without dependencies be both reading two operands and writing back a result every clock, then you've suffered a performance loss compared to a machine which can. \$\endgroup\$ – Chris Stratton Feb 3 '18 at 23:16
  • \$\begingroup\$ depends on the design. I agree with you in general but am well versed in a design that does not have this problem. \$\endgroup\$ – old_timer Feb 4 '18 at 0:27
  • \$\begingroup\$ to be fair do you consider read and write in the same cycle as single ported or dual? I cant imagine the OP is concerned about this, more about sanity and success rather than high performance. and a register file (however many ports) would aid in that. \$\endgroup\$ – old_timer Feb 4 '18 at 0:32
  • \$\begingroup\$ Simultaneous read/write requires two ports. There may be specialized (vs general purpose) dual-port rams where each port only has a given role, but in terms of general purpose parts a full DPR would be required - and for full two operand capability, two of them written in parallel. \$\endgroup\$ – Chris Stratton Feb 4 '18 at 0:35
  • \$\begingroup\$ we no reason why D and Q of the flip flop have to be tied to the same logic, if you call that dual then fine. \$\endgroup\$ – old_timer Feb 4 '18 at 0:45
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Using a (modern) SRAM chip with 74LS' based CPU is a bit like filming Exodus and someone in the film is wearing a digital watch. ( The SRAMS avail. back then are not around anymore like 74LSxx parts, so modern SRAMs did not exist, but then this is the only reasonable compromise. )

It's called an anachronism, an object misplaced in time.

My favorite book "The Soul of a New Machine" described the puckish journey of Engineers and their manager at Data General who made history with "the Eagle" just before the mid late 70's when CMOS came out.

It was the same era, I started life as an Engineer with experience of designing a UART board from 74LSxx's because Rotamola had yet to release its MC6821. I designed it on paper in a week and did the layout on a 4 layer board with those 44 pin edge connectors to the MC6800 card and it worked on the first spin. Another card fanned out to 128 outputs and 128 inputs on the main console that lit up like a house at Xmas with all the engraved square backlit pushbuttons.

But like "Exodus" your design will still be a classic, just like Steve at GRC and the homebrew PDP8 users.

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  • \$\begingroup\$ No, Static RAM dates to the mid 1960's, and some parts even existed within the 74LS family. The PMOS 1101 was on the market in 1969 and the CMOS 5101 appears in the 1975 Intel literature \$\endgroup\$ – Chris Stratton Feb 4 '18 at 7:12
  • \$\begingroup\$ I agree those parts would not be anachronisms. But I assumed he was not choosing those. \$\endgroup\$ – Sunnyskyguy EE75 Feb 4 '18 at 7:21
  • \$\begingroup\$ Further, Kidder's book is about events of the late 1970s, specifically the second attempt to create a successor to the 1974 16-bit Eclipse. It would appear most of the story took place in 1978 and/or 1979, with the product released in 1980. \$\endgroup\$ – Chris Stratton Feb 4 '18 at 7:25
  • \$\begingroup\$ OK It was I who came out before the book in the mid '70's, I guess the DataGeneral minicomputer in my lab in '75 was the 1st generation and I didn't read the book until long I after I left my 1st job in '79. But if any '70's era SRAM's are still in production, I'd be surprised. \$\endgroup\$ – Sunnyskyguy EE75 Feb 4 '18 at 7:35
  • \$\begingroup\$ nteinc.com/specs/2100to2199/pdf/nte2114.pdf \$\endgroup\$ – Bruce Abbott Feb 4 '18 at 18:23

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