# Question about noise effects of parasitic common-mode coupling in a single ended system

This question is related to a previous question. Now I'm trying to understand a bit deeper about the phenomenon I will present.

(to see bigger view please left click)

To make it clear enough I used a simplistic model instead of a real switching power supply model I made up for a AC/DC flyback converter since I'm not able to draw or model an entire SMPS. For simulation, I chose the neutral as AC ground and for the reference for the entire circuit system. I also tied the neutral to the earth far away at some point.

All values are arbitrary. AC 150 VAC 50Hz mains is rectified by the bridge and C1. M1 is the PWM switching transistor. Left side and right side is divided by galvanic isolation i.e transformer.

Since I chose the entire simulation's ground as AC_GND, so for the DC side's ground DC_GND I added a very high Rgg between the AC_GND and DC_GND to define a new ground as DC_GND.

Cp1 and Cp2 represents the AC mains parasitic capacitances and their effects appears as follows at terminal A and B wrt earth:

Above V(a) and V(dc_gnd) are the voltages at terminals A and B wrt earth and V(A,DC_GND) shows the differential voltage between these terminals. Up to now was to model a power supply which causes ghost common-mode voltages.

Now to mimic the real scenario, I will add a very simple transducer(a voltage divider) across the terminal A and B and the output of it will go to a "single-ended earth grounded" data-acquisition board's channel 1.

Then I will add another single-ended voltage source which is 1V DC to data-acquisition channel 2.

Below represents what I mean with these:

(to see bigger view please left click)

I added Rw, Rw1 and Re resistors which represents possible resistances between wiring resistances and earth ect. And here the plots for Vch1 and Vch2 wrt to data-acquisition's own ground DAQ_GND:

The 1V DC source above is affected due to the common-mode voltages passing through the resistors. This also corrupted the differential voltage signal of Ch1 same way.

My question:

In my previous question, I had written that whenever I connect Vch1(force-transducer) to one of the daq's channels another transducer signal's standard deviation and noise floor increases. And when I remove Vch1, Vch2 then becomes almost noiseless.

I'm very curious; can that be my simulation/schematics and conclusion correct? Can it be the reason for the increase in noise amplitude and increase in standard deviation? I mean my conclusion is when the common-mode current flows through the grounds it causes this noise due to the resistances?

Also when I make the FFT of the noise it is obviously 50Hz and harmonics. But I thought 50Hz noise wouldn't affect standard deviation(?).