# How to design ultra low-power opamp?

I am designing a low-power opamp (differential amplifier) that will be used in the low-power consumption devices, e.g., power management circuits, portable devices, or energy harvesting circuits. I am new to this area and not any expert, but this idea just came to my mind after taking an Analog Circuits course at my university.

I thought the power consumption would be around 200 uW, and operating voltage would be around 1.3-5 V. Thus the maximum quiescent current would be 200uW/5V = 40 uA. The following is the general idea of the above features rewritten:

1. Maximum quiescent current ~40 uA
2. Operating voltage 1.3-5 V
3. Gain bandwidth product ~500 kHz

I have searched through many textbooks and have done several SPICE circuit designs, but still couldn't achieve the above features with a good stability characteristic. (For example, the bias and start-up circuit in my design consumes a significant amount of quiescent current even operating at 1.3 V. Or when I tried to improve the stability by adding compensation network, the gain bandwidth dropped below a few of 10 kHz.) I also tried to reverse engineer some chip like TSU111 but the schematic is not revealed (unlike the ubiquitous 741 opamp which is quite well-known ?). It seems to me that it is almost impossible to reverse engineer the commercial chips out there.

1. Is this just a secret of the company or is it just an ongoing topic in the research area?

I know this question is too broad. But I would like to ask some of the good practice or the general procedure in "designing/reverse engineering" the low-power opamp like in the commercial chips. The answer could be any that answers the following questions:

1. What considerations should I take into account in the low-power design? (Operating in the subthreshold region to get a low quiescent current? Adding more stages to get more gain, but that means more quiescent current and thus power consumption?)
2. Where in the circuit should I first start sizing the W/L ratio of the MOSFET? (I usually start at the bias circuit and try to size the W/L ratio to get the current that meets the specifications that I want. Any other considerations?)
• 500kHz BW (in which case you'll also need a DC gain) or GBW? What is the load capacitance? How is it configured (feedback)? Is it an OTA or really an opamp? – Sven B Feb 4 '18 at 10:54
• You're asking for a Iq * GBW 50% better than a state-of-the art commercial design. I imagine you'll have to start hitting the patent papers and even then.. – Spehro Pefhany Feb 4 '18 at 11:45
• @SpehroPefhany Well, at a supply of 1.3V yes, but at 1.5+ there's always the TSV6290 which at 30uA and 1.3MHz GBW (caveats) is pretty close or for higher voltages, there's the MIC860 which can hit 4MHz @ 30uA. So it should be possible, it'd just be really hard. – Sam Feb 4 '18 at 19:43
• @SpehroPefhany But thanks for your Iq * GBW in your sentence. I never heard it and just now read about the trade-off between the gain-bandwidth product and the quiescent current! – IgNite Feb 4 '18 at 19:56
• The actual figure of merit includes at least a $C_L$ as well. Usually along the lines of: $FoM=C_L \cdot GBW / I_{ds}$ – Sven B Feb 5 '18 at 7:22

There is nothing special about ultra-low power OTAs/OpAmps. Of course you can use a few tricks to improve the power consumption, but also standard textbook circuits can be designed to work with low power consumption.

The ultimate limits are speed and leakage currents which depend on the given technology. Usually 40uA is not considered ultra-low power, as such designs consume typically less than 1uA in total.

A few ideas to get you started: Low power implies low speed, therefore you need to consider the load, which is usually capacitive. For a given bandwidth a certain transconductance will be required to drive the capacitance. A relationship like GBW = (gm/(2*pi*C) will result.

Say we have an ultra-low power design and we want to drive 200fF and achieve a GBW of 1MHz. A gm of 1e6 * 2*pi *200e-15 ~ 1.3uS will be required. To keep things simple we use a telescopic OTA where (nearly) all the current can be used to generate a transconductance.

For ULP designs we aim at an gm/Id ratio of at least 20. Since we have two transistors in the input stage we will need twice the current which results in 1.3uS / (10uS/uA) = 130nA.

If we wanted to drive 1pF (=5*200fF) or we wanted to achieve a GBW of 5MHz (=5*1MHz) then 5 times the current would be required. The transistors will also introduce parasitic capacitances so a higher current will be required.

Suppose you want precision matched input FETs; assume Cgate is 1pF each. To turn that FET on/off with 1uA current, with delta_Vgate of 1 volt, the time will be (starting with I = C * dV/dT)

dT = I/(C*dV) = 1uA/(1pF * 1volt) = 1 microsecond.

Now, just how ultra-low-power must your opamp be?