Declaring vector variable in the Verilog not starting with the MSB(e.g,. reg var[0][20])

Question

I am familiar to the syntax described in here

net_type [msb:lsb] list_of_net_identifiers;

reg [msb:lsb] list_of_register_identifiers;

For example, to declare the 32bits memory address, I could use the syntax like

reg [31:0] address;

Also to declare the memory comprised of the 16 elements which consist of 32 bits each,

reg [31:0] mem [15:0]; 

However, I could frequently face the syntax like below to declare multidimensional arrays.

reg [31:0] mem [0:15]

I've googled it and found one related article in here. It seems that whether the larger number comes first or not, the first number before the colon (:) is the MSB and the LSB follows. It seems like the difference comes from the preference of coding.

However, I think mixing [31:0] and [0:15] style is little bit count-intuitive and confusing even though it depends on the preference. I could see a lot of mixing especially in the declaration of multi-dimensional arrays. Why is it allowed to be used? Is there any advantage that I couldn't notice?

Answer 1

In Verilog, the numeric index ordering of a memory is only a matter of preference except when loading the memory from a text file. The first line in the file represents the left index, and like most other languages, starts at 0, so [0:15] is the more common way to declare a memory range. Otherwise there is no advantage one way or the other in how you declare a memory range since you canny only reference one memory element at a time.

The same can be said about a vector if you never plan to access individual bits of the vector. But once you do, how you address each bit becomes significant in position of an integral value.

In SystemVerilog, the ordering of both the vector width and memory dimensions becomes significant because you can stream memories as a whole and well as selects parts just like you do a vector.