# Declaring vector variable in the Verilog not starting with the MSB(e.g,. reg var[0][20])

I am familiar to the syntax described in here

net_type [msb:lsb] list_of_net_identifiers;

reg [msb:lsb] list_of_register_identifiers;

For example, to declare the 32bits memory address, I could use the syntax like

reg [31:0] address;


Also to declare the memory comprised of the 16 elements which consist of 32 bits each,

reg [31:0] mem [15:0];


However, I could frequently face the syntax like below to declare multidimensional arrays.

reg [31:0] mem [0:15]


I've googled it and found one related article in here. It seems that whether the larger number comes first or not, the first number before the colon (:) is the MSB and the LSB follows. It seems like the difference comes from the preference of coding.

However, I think mixing [31:0] and [0:15] style is little bit count-intuitive and confusing even though it depends on the preference. I could see a lot of mixing especially in the declaration of multi-dimensional arrays. Why is it allowed to be used? Is there any advantage that I couldn't notice?