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I often see the block structure of NOR with source line for every pair of cells: enter image description here

However, in this answer there is a design with source line for every cell. It confuses me because in this case I can see no resemblance with NOR gate at all.

Is it a different kind of FLASH NOR design or is it just wrong use of terminology?

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  • \$\begingroup\$ I just found this great article which describes the picture as DINOR design and compares it to others in Figure 10-17. But the terminology is still mysterious to me: DINOR resembles NOR gate and NOR FLASH looks like DRAM, not as NOR at all. \$\endgroup\$ – Jan Turoň Feb 4 '18 at 11:39
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I just figured out that the resemblance with NAND and NOR is not physical, but logical in reading process. To read a value from WLx

  • in NAND we set the voltage to all WLs but the one we want to read high enough to enable current between source and drain regardless the charge on the floating gate (Von). On the examined WL The voltage is set between 1 and 0 threshold voltage, so the BL value is logically 1*1*x*1*1... (where x is the examined bit) which is AND function
  • in NOR we set Voff (no current regardless the FG charge) to all WLs but the examined one, so the BL value is logically 0+0+x+0+0... which is OR function in both NOR (DRAM cells physical resemblance) and DINOR (shown in the question) design

On SLC FG MOSFETs the values are actually inverse (0 has higher threshold voltage than 1), so NAND and NOR names make sense now.

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