I'm getting pretty deep into MCU design and I've run into a problem for which I'd like to find a formula.
In circuit path design how can I correlate max wire length to max transmission frequency on that wire/pin?
I'm working with a wide assortment of MCUs and external hardware operating range 16MHz to 160MHz.
For example: I have a 20MIPS MPU interfaced with an SRAM (parallel) IC. The SRAM has a 10ns access speed which is more than enough speed for the MPU. The MPU takes two intsructions one to write the address and one to read/write the data. The data and addresses are on separate buses so the maximum speed on any given pin in the project is 10MHz. Currently that works just fine with a 4" ribbon wire for each bus, but I'm concerned that If I swap out MCUs for a 48MIPS or 72MIPS MCU that I will have timing issues.
I read this thread and a few others, but they appear to be mostly single use fixes, where I need a general formula if possible. Wire length, EMI and comms failures
Followup question, does it matter if the signal is part of a parallel or serial bus, or can each pin simply be examined as a single entity?
Alternately acceptable to a formula would be some good reading material on this specific topic.
I also recognize that using larger gauge wire, twisted pair for serial, adding a ground line(s) for noise, and using pull-ups/downs may help the issue. For this question though my primary focus is length v frequency, if that's possible.
Thanks a bunch