FPGAs can easily run at 100 to 500 MHz and create time resolutions of 10 to 2 ns. That frequency can be used to create timestamp counters, which are in turn used to create very fine grained time measurements / timestamps for profiling.

However, these counters rely on an external oscillator and sometimes also on internal clock modification blocks (CMBs like PLL, MMCM, ...). External oscillators have a precision or jitter of 50 (20) ppm at 100 Mhz reference frequency. This gives a possible time error of 50 us per 1 second.

In a customer's system, multiple FPGA boards are coupled via Ethernet and PTP (Precision Time Protocol). One board acts as a server, the others as slaves. PTP can synchronize 2 stations within 10 ns accuracy, whereas the FPGA based master and slaves can not hold the time precision between PTP updates.

Is there any way to increase the timestamp counter accuracy in an FPGA (Zynq UltraScale+) to below 10 us?

Is it possible to measure time drifts (wander) and adjust the timestamp counter?

  • \$\begingroup\$ 50 ppm is a frequency drift spec. Jitter is likely orders of magnitude higher. \$\endgroup\$
    – The Photon
    Feb 5, 2018 at 1:16
  • \$\begingroup\$ What is this timestamp counter you're referring to? PTP has most definitely been implemented on FPGAs, but there is usually a specialized, high precision (fractional) PTP clock. This is relatively simple to implement in HDL, but integrating it with the rest of the system is a different story. \$\endgroup\$ Feb 5, 2018 at 17:26
  • \$\begingroup\$ After having done two PTP updates, you have all knowledge of how much the board drifts. So from there, what prevents you to apply a correction factor on the timings? If this is a data acquisition board, you can apply a sample rate conversion algorithm. Problem solved in the digital domain. Cheap. \$\endgroup\$
    – dim
    Feb 5, 2018 at 17:30

2 Answers 2


You can get better oscillators: reasonably cheap temperature-compensated crystal oscillators (TCXO) can reach 1 PPM.

Some TCXO can be steered with a control voltage (a VCTCXO). You can count the clock cycles of your TCXO with the FPGA and discipline it to a GPS 1PPS signal or PTP. You will have to figure out a good feedback law between the count minus the PTP value and the control voltage. The response time of the loop must be picked wisely.

There is an open-source design from CERN using that method. Checkout page 2 on the schematics


Your question is rather vague and rambling, and contains what appears to be a few misconceptions, so I'll just offer some broad thoughts here, based on my work in time transfer and synchronization across telecom networks.

A local clock will have some nominal frequency error relative to some standard. If the frequency can be adjusted (e.g., VCXO), the frequency error can be driven to zero using a PLL. This can be done in hardware or software. If you can't adjust the oscillator directly, you can use DDS techniques to synthesize a corrected clock.

However, that leaves you with a residual phase error, the magnitude of which depends on the nature of your phase detector. A discrete-time phase detector will not be able to resolve phase errors that are smaller than the period of the signals driving it. A continuous-time phase detector will be able to do better than this, with the ultimate limit driven by the analog noise in the system.

PTP uses hardware timestamps on the packets that are exchanged among the nodes in order to estimate the network delays associated with each link. This information is used to estimate both the time offset and the frequency error of the local clock, which is then used to synthesize a "virtual" timebase that is locked to the network master.

Crystal oscillators actually have very good short-term stability and low jitter — some of them even have better specs than atomic standards in this area. The only thing they lack is absolute frequency accuracy, which means that they cannot serve as "primary" standards.

If you can offer more details about what you're trying to accomplish as well as the technology and constraints that you are working with, I can respond with more specific advice.


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