FPGAs can easily run at 100 to 500 MHz and create time resolutions of 10 to 2 ns. That frequency can be used to create timestamp counters, which are in turn used to create very fine grained time measurements / timestamps for profiling.
However, these counters rely on an external oscillator and sometimes also on internal clock modification blocks (CMBs like PLL, MMCM, ...). External oscillators have a precision or jitter of 50 (20) ppm at 100 Mhz reference frequency. This gives a possible time error of 50 us per 1 second.
In a customer's system, multiple FPGA boards are coupled via Ethernet and PTP (Precision Time Protocol). One board acts as a server, the others as slaves. PTP can synchronize 2 stations within 10 ns accuracy, whereas the FPGA based master and slaves can not hold the time precision between PTP updates.
Is there any way to increase the timestamp counter accuracy in an FPGA (Zynq UltraScale+) to below 10 us?
Is it possible to measure time drifts (wander) and adjust the timestamp counter?