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In ModelSim, I can click compile and ModelSim will compile it quickly, around 1 or 2 seconds.

But in Quartus Prime, I need to run Analysis & Elaboration or Analysis & Synthesis which runs more than 40 seconds for the same code which takes only 1 or 2 seconds to compile in ModelSim.

I know Analysis & Synthesis will perform Synthesis as well, but sometimes I need to just check whether my code has error or not without the need to synthesis.

Until now, I have been going back and forward between those two CAD tools.

Any suggestion will be appreciated.

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For doing FPGA development, you really don't want to synthesize your code until you have simulated it and verified that it works. From your comments about modelsim, it seems you are mostly doing that, so I'd recommend using modelsim to check for syntax errors in your code, and only move to quarts when you are satisfied that it's correct.

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  • \$\begingroup\$ I think the "synthesis" here the OP is referring to is the RTL synthesis stage required for the RTL simulation in Modelsim. In some cases (such as this), it's necessary to pre-synthesize the code before running simulation. \$\endgroup\$ – stanri Feb 13 '18 at 12:35
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The reason why the Quartus Prime synthesis stage is taking longer is because it is also synthesizing from scratch all of the IP-cores and other IP you are using in your code, including all of the relevant Altera library files.

When you re-start the simulation in Modelsim, it only synthesizes the files in your project. Going back and forth every time you make a change is a mission, so I've figured out a quicker way:

I don't know how your modelsim is setup, but my modelsim has 3 types of files.

  • "work" library files, where I add all my testbench stuff. These are the only files that modelsim compiles (which is why it's so quick).
  • "rtl_work" which is where Quartus puts all my project files that it's compiled. Modelsim doesn't compile these because they're already compiled.
  • The other pre-compiled libraries after that. Modelsim doesn't compile these.

See, here:

Modelsim libraries

When you run the "Analysis & Synthesis" stage in Quartus, it will re-compile ALL of the "rtl_work" libraries and all of the other ones that are relevant. If you make a change to a file in the "rtl_work" section, it won't reflect in the simulation. So, here's the trick:

If you want modelsim to pick up your changes:

1) DELETE the file from the the rtl_work section. (don't worry, it will be back as soon as you run the "Analysis & Synthesis" again). Do this by right-clicking on the file under rtl_work and choosing "Delete".
2) ADD it to your project (in the usual way: Under project tab, right click -> "Add to project" -> "existing file").

This way, your file will be moved from "rtl_work" to "work", and modelsim will pick up the changes to your file that you're debugging. You can now just use the modelsim re-run simulation when you make a change instead of re-running the whole quartus thing.

Remember, if you change an IP core settings, you do need to re-run Quartus because those are different and live under the pre-compiled libraries.

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  • \$\begingroup\$ hi, thanks for your help. I haven't gotten a change to try your suggestion because I still have other exams. I will try that later. \$\endgroup\$ – Codelearner777 Feb 22 '18 at 9:40

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