The reason why the Quartus Prime synthesis stage is taking longer is because it is also synthesizing from scratch all of the IP-cores and other IP you are using in your code, including all of the relevant Altera library files.
When you re-start the simulation in Modelsim, it only synthesizes the files in your project. Going back and forth every time you make a change is a mission, so I've figured out a quicker way:
I don't know how your modelsim is setup, but my modelsim has 3 types of files.
- "work" library files, where I add all my testbench stuff. These are the only files that modelsim compiles (which is why it's so quick).
- "rtl_work" which is where Quartus puts all my project files that it's compiled. Modelsim doesn't compile these because they're already compiled.
- The other pre-compiled libraries after that. Modelsim doesn't compile these.
When you run the "Analysis & Synthesis" stage in Quartus, it will re-compile ALL of the "rtl_work" libraries and all of the other ones that are relevant. If you make a change to a file in the "rtl_work" section, it won't reflect in the simulation. So, here's the trick:
If you want modelsim to pick up your changes:
1) DELETE the file from the the rtl_work section. (don't worry, it will be back as soon as you run the "Analysis & Synthesis" again). Do this by right-clicking on the file under rtl_work and choosing "Delete".
2) ADD it to your project (in the usual way: Under project tab, right click -> "Add to project" -> "existing file").
This way, your file will be moved from "rtl_work" to "work", and modelsim will pick up the changes to your file that you're debugging. You can now just use the modelsim re-run simulation when you make a change instead of re-running the whole quartus thing.
Remember, if you change an IP core settings, you do need to re-run Quartus because those are different and live under the pre-compiled libraries.