First question

Whether we declare the array as scalar or vector, we can access each element bit by bit. For example, we can declare two arrays below.

reg scalar_array[0:9];
reg [0:9] vector_array;  

always @*
  scalar_array[0] = 1'b1;
  vector_array[0] = 1'b1;

I would like to know if the difference exists between two declarations.

Second question

Also, when I declare the two-dimensional array like below, I could access the entire row using the indexing operator[] for the variable declared using a below syntax.

reg[X:X] var_name [Y:Y];  

However, I couldn't access the entire row when I declare the array using the below syntax.

reg var_name [X:X][Y:Y];

I would like to know how this concept can be synthesized on the hardware, and if they are both synthesizable, what is the difference between them.

reg [0:9] vector_array_2d [0:15];
reg scalar_array_2d[0:9][0:15];
always @*
  vector_array_2d[0] = 'd1;
  scalar_array_2d[0] = 'd1; //raise the error!! 

For your first question, search for the difference between packed and unpacked arrays.

Your second question is a Verilog limitation with unpacked arrays - it only allows access to one array element at a time. SystemVerilog does not have this restriction. You can access an unpacked array as a whole, or select an entire dimension.

| improve this answer | |
  • \$\begingroup\$ Thanks for an answer. However, it seems that Verilog doesn't support multiple packed dimensions. Vivado raise the error when I tried to declare the packed array like reg[3:0][4:0] packed_array; \$\endgroup\$ – JaeHyuk Lee Feb 5 '18 at 5:23
  • \$\begingroup\$ Make sure you have turned on SystemVerilog, use a *.sv file extension. \$\endgroup\$ – dave_59 Feb 5 '18 at 5:25

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