# What is the difference between scalar array and vector array?

First question

Whether we declare the array as scalar or vector, we can access each element bit by bit. For example, we can declare two arrays below.

reg scalar_array[0:9];
reg [0:9] vector_array;

always @*
begin
scalar_array[0] = 1'b1;
vector_array[0] = 1'b1;
end


I would like to know if the difference exists between two declarations.

Second question

Also, when I declare the two-dimensional array like below, I could access the entire row using the indexing operator[] for the variable declared using a below syntax.

reg[X:X] var_name [Y:Y];


However, I couldn't access the entire row when I declare the array using the below syntax.

reg var_name [X:X][Y:Y];


I would like to know how this concept can be synthesized on the hardware, and if they are both synthesizable, what is the difference between them.

reg [0:9] vector_array_2d [0:15];
reg scalar_array_2d[0:9][0:15];
always @*
begin
vector_array_2d[0] = 'd1;
scalar_array_2d[0] = 'd1; //raise the error!!
end


For your first question, search for the difference between packed and unpacked arrays.

Your second question is a Verilog limitation with unpacked arrays - it only allows access to one array element at a time. SystemVerilog does not have this restriction. You can access an unpacked array as a whole, or select an entire dimension.

• Thanks for an answer. However, it seems that Verilog doesn't support multiple packed dimensions. Vivado raise the error when I tried to declare the packed array like reg[3:0][4:0] packed_array; – JaeHyuk Lee Feb 5 '18 at 5:23
• Make sure you have turned on SystemVerilog, use a *.sv file extension. – dave_59 Feb 5 '18 at 5:25
• this answer is specific to SystemVerilog, not Verilog – Aaron Thomas Aug 12 at 16:19
• – Aaron Thomas Aug 12 at 16:26
• @AaronThomas SystemVerilog introduced the terminology "packed"and "unpacked", the functionality was the same as in Verilog. Although Verilog only allows a single packed dimension. – dave_59 Aug 12 at 16:28

For the first question, the difference lies in how the register is to be treated - as either a bus (a single value, wider than one bit) or an array (multiple values, stored under one name). It seems a little bit philosophic, but this answer provides more detail.

For the second question, it may rely on the manufacturer or provider. For example, Xilinx Vivado will synthesize multi-dimensional arrays of up to two dimensions only (ref UG901).