Need help understanding the status output generation of an ALU

Question

I'm currently trying to implement a simple processor using Verilog in a FPGA. I'm using Mic - 1 architecture as a reference model.

The thing I can't understand is the ALU is generating a "status" output when a certain operation is completed. How the ALU exactly know a certain operation is completed? Because each operation may take different number of clock cycles to complete. For example multiplication may take many clock cycles than single addition because multiplication need several bit shifting and additions.

Is this time delay should be pre-defined in ALU?

MIC-1 architecture is shown below.

Answer 1

Your ALU will have a state machine which performs any multi-cycle operations. This state machine is what controls the 'end' of an instruction.

There is no reason that operations must take more than one cycle, but as soon as you permit this, you need to track phases of a single instruction. You might also want to consider the impact of stalling on either instruction fetch or data load/store (since you are soon likely to come across bus infrastructure which involves arbitration) - these can maybe give you some ideas about what can work in 'lock-step' and when you need to wait.

The architecture you show here looks like a single stage, with no pipelining. There is no reason why your ALU can't consume multiple cycles, and allow the rest of the machine to advance only once it's stable.

A multi-cycle stage will either be clocked (shift/operate for each bit), or a single deep combinatorial path (which will be harder from a synthesis constraint point of view). Typically, you might try and make your slowest path an easy multiple of the input, and maybe stall for 3 cycles (as an example). Sometimes you can look at a couple of input data bits to decide how much time the logic needs to become stable.