I'm currently trying to implement a simple processor using Verilog in a FPGA. I'm using Mic - 1 architecture as a reference model.
The thing I can't understand is the ALU is generating a "status" output when a certain operation is completed. How the ALU exactly know a certain operation is completed? Because each operation may take different number of clock cycles to complete. For example multiplication may take many clock cycles than single addition because multiplication need several bit shifting and additions.
Is this time delay should be pre-defined in ALU?
MIC-1 architecture is shown below.