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I'm confused about the transfer function of a digital phase frequency detector. Why can we say that the pfd output is proportional to the phase error?

The pfd (with charge pump) generates current pulses of fixed amplitude \$I_{CP}\$ like it is described for example here. For small phase deviations the length of these current pulses is proportional to the phase difference of the input signals. So the pfd output current is clearly not proportional to the phase error.

On the other hand, the transfer function of a digital PFD is said to be \$K(s) = \frac{I_{CP}}{2\pi} = \frac{I_{out}(s)}{\Delta \phi(s)}\$. In this sense the pfd generates a current proportional to the phase error.

Why is this not a contradiction?

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The pfd (with charge pump) generates current pulses of fixed amplitude ICPICP like it is described for example here. For small phase deviations the length of these current pulses is proportional to the phase difference of the input signals. So the pfd output current is clearly not proportional to the phase error.

Since the duty cycle is proportional to the phase error, and the amplitude of the pulses is fixed, when averaged over several cycles the output voltage or current is proportional to the phase error.

Since the control loop bandwidth is typically orders of magnitude lower than the clock frequency, this means the PFD output is proportional to the phase error when considering frequencies within the operating band of the control loop, which is what matters for modeling the control loop.

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  • \$\begingroup\$ Is this the reason why it is recommended to choose the loop bandwith to be max 1/10 of the pfd frequency? \$\endgroup\$ – user2224350 Feb 5 '18 at 21:19
  • \$\begingroup\$ @user2224350, fundamentally, you only get new information about the phase error once per cycle of the reference clock. So you shouldn't expect to be able to be able to adjust the VCO and check the error any faster than that. Using a loop BW 1/10 the ref clock frequency lets you average several phase error measurements before making an adjustment, and also makes sure the phase delay in the full-frequency part of the circuit doesn't affect your control loop stability. \$\endgroup\$ – The Photon Feb 5 '18 at 22:47
  • \$\begingroup\$ Do you have any source about the relation of pfd frequency and loop bandwith? \$\endgroup\$ – user2224350 Feb 5 '18 at 23:09
  • \$\begingroup\$ @user2224350, my experience is mostly with output frequencies above 1 GHz, so that may color what I know about. But common sense says if you want smooth a PWM signal (the PFD output) you need to average over more than just a couple of cycles. \$\endgroup\$ – The Photon Feb 5 '18 at 23:21
  • \$\begingroup\$ Floyd Gardener wrote a book on PLLs, wherein he uses z-transforms to show 1/10 is preferable, but 1/5 may work depending upon any higher order poles in the response. \$\endgroup\$ – analogsystemsrf Feb 6 '18 at 4:02

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