# How output signals connect when they are from different chips and banks

First I apologize for such an ambiguous title. I am reading Code by Charles Petzold during my leisure time and have a question that I can't figure out by myself.

It is about Chapter 21, in which Code tries to build a RAM for 8080 processor out of memory chips 2012. To summarize, 8080 has 16-digit addresses, 8-digit data input and output respectively, while 2012 has 10-digit addresses, 1-digit data input and output respectively. Hence, eight of 2012 chips are wired together to store the entire 8-bit, and such 8-chip group is called a bank. Each memory board consists 4 of such banks.

Then, because we have 4 banks,

If you recall the messy details of combining RAM arrays in Chapter 16, you might assume that we also need eight 4-to-1 Selectors to select the correct data output signals from the four banks of memory. But we don't, and here's why

Here comes my first question:

1. Why do we need EIGHT 4-to-1 selectores? 8 chips are wired together as a whole, and their signals are the same as other ones in the same bank. More precisely, I know 8 of them work, but I am wondering whether ONE is enough. (I understand we are not using 4-to-1 selector, just want to finish the thought experiment).

Then, it explains why:

Normally, the output signals of TTL-compatible integrated circuits are either greater than 2.2 volts (for a logical 1) or less than 0.4 volts (for a logical 0). But what happens if you try connecting outputs? If one integrated circuit has a 1 output and another has a 0 output, and these two outputs are connected, what will result? You can't really tell, and that's why outputs of integrated circuits aren't normally connected together.

I understand the part that circuits are not normally connected together. The question however is

1. When had we connected them if we ever followed 4-to-1 selector design? Were we not using an OR logic gate? (Again, I know we are not using this design, just want to make sure what would've happened if we had done it.)

A rough diagram that I have in mind is as follows (I am not sure if it is clear enough, if not, could some one points me a online diagram website and I'll try to make it as clear as possible):

• Welcome to EE.SE. Please refine your questions to just the important ones. Idle speculation is something we do not have time for. Have you looked up 4 to 1 or 2 to 1 mux decoders? Please do some research of your own.
– user105652
Feb 6, 2018 at 0:28
• Thanks for your comment. However I have done my work. I do know what it is a 4-to-1 selector - if you look at the left top corner there is a selector (made up of 2 switches). If you could read my question more patiently, you should find out I am not having idle speculation (at least I drew the diagram. If it is too trivial for you, I would much appreciate it if you can explain them in one or two sentences.). Feb 6, 2018 at 0:42
• @jsotola Code is trying to build a computer from scratch.Before this point, only 2-state selectors introduced. He tries to explain two outputs should not connect to each other, and a buffer is needed. <-I get all these parts and know in reality we do not multiplex the outputs. However, in this particular case, even if 2012 had only two states, I think we can avoid connect two of them by an OR gate. I.E. his reasoning doesn't persuade me as of why we not use multiplex for the outputs (the outputs do not connect directly). I'd like to know which parts of my thoughts are wrong Feb 6, 2018 at 2:01
• @jsotola thank you for comments. I guess I didn't make myself clear. Let me try again. Code is trying to explain why we use tri-state design instead of 4-to-1 selector (Or why not multiplex outputs). Although we use 2012 as an example, at this point, we are assuming a 2012 without the tri-state (only after explaining undefined behavior of connecting two outputs, he introduced tri-state). However, I do not see the disadvantage of using normal 2-state chips because we can use OR gate instead of connecting output signals together. Please let me know if I am making the question a little clearer. Feb 6, 2018 at 4:54
• i understand now, i think .... tri-state memory chips would use less external circuitry. ... the delay through the OR gate or through the multiplexer would add to the "access time" ... with the OR gate arrangement the memory chip output would have to be guaranteed to be LOW for all chips that are not being read Feb 6, 2018 at 5:08