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I am checking what I can and cannot do in aggregating and concatenating in VHDL.

while I can combine two vectors by concatenating them, I keep getting error if I use aggregate.

I saw one answer here shows it is possible.

Can someone explain why they are giving errors, or maybe it is the language which does not allow this?

I appreciate any suggestion.

here is my code. I marked the correct and the wrong lines.I use ModelSim. I comment/uncomment when checking to avoid multiple drivers.

architecture RTL of example_array is
--signal Z_BUS                                  : std_logic_vector(7 downto 0);
--signal R_BUS                                  : std_logic_vector(3 downto 0);
--signal A_BIT, B_BIT, C_BIT, D_BIT     : std_logic;

signal T_BUS                                    :  std_logic_vector(7 downto 0);
signal Y_BUS                                    :  std_logic_vector(7 downto 0);
signal U_BUS                                    :  std_logic_vector(3 downto 0);
signal P_BUS                                    :   std_logic_vector(3 downto 0);
signal E_BIT, F_BIT, G_BIT, H_BIT       :  std_logic;

BEGIN
Z_BUS <= A_BIT & R_BUS & B_BIT & C_BIT & D_BIT;                 -- correct
--Z_BUS <= W_BUS & R_BUS;                                       -- correct

P_BUS <= (E_BIT, F_BIT, G_BIT, H_BIT);                          -- correct
U_BUS <= (E_BIT, F_BIT, G_BIT, H_BIT);                          -- correct


(E_BIT, F_BIT, G_BIT, H_BIT)    <= std_logic_vector'("1011");       -- correct
(E_BIT, F_BIT, G_BIT, H_BIT)    <= P_BUS(3 downto 0);               -- correct
(E_BIT, F_BIT, G_BIT, H_BIT)    <= P_BUS;                           -- correct
Y_BUS <= (2 => '1', 3 => F_BIT, 1 downto 0 => '0', others => '0');  -- correct

--T_BUS(7 downto 0) <= (U_BUS(3 downto 0), P_BUS(3 downto 0));  -- WRONG!!
--T_BUS <= (U_BUS, P_BUS);                                      -- WRONG!!
--(U_BUS(3 downto 0), P_BUS(3 downto 0)) <= T_BUS(7 downto 0);  -- WRONG!!

END architecture RTL;
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  • \$\begingroup\$ (U_BUS(3 downto 0), P_BUS(3 downto 0)); is an aggregation not a concatenation (e.g. T_BUS <= U_BUS & P_BUS;). For the aggregate assignment you haven't specified the VHDL version, earlier than or -2008 type nybble_array is array (0 to 1) of std_logic_vector(3 downto 0); and (U_BUS, P_BUS) <= nybble_array'(T_BUS (7 downto 4), T_BUS (3 downto 0)); You need an element on the right for each element on the left. The type has to be discernible from context. The element type has to be the same. \$\endgroup\$ – user8352 Feb 7 '18 at 19:50
  • \$\begingroup\$ You are asking for decomposition, not aggregation ... I know that the LRM calls it "aggregate" in the BNF of target. That's because the LRM is somehow lazzy in reusing existing BNF rules. But the technical correct term is decomposition, when a aggregate appears on the left side of an assignment. \$\endgroup\$ – Paebbels Feb 10 '18 at 22:57
  • \$\begingroup\$ @Paebbels - IEEE Std 1076-2008 describes design model structural decomposition, VHDL is a hardware description language. The term is not found in the Glossary of Software Engineering Terms (IEEE Std 610.12-1990) of the era the VHDL standard was created while 610.12-2012 defines it as 2. the partitioning of a modeled function into its component functions. That doesn't fit well with assignment as an impenetrable basic operation (5.1). The VHDL Extended BNF describes syntax which for an aggregate remains the same whether used as an expression or assignment target. \$\endgroup\$ – user8352 Feb 16 '18 at 18:32
  • \$\begingroup\$ @user8352 I know what the text in VHDL LRM says. I'm the vise-chair of the IEEE P1076 working group ... The term aggregate mean "collection". That is true for the right hand side of an assignment, but not for the left hand side (LHS). The LHS is the reverse operation - a split operation. It is called decomposition or unpacking. The correct way in the VHDL LRM would be to have a e.g. decomposition BNF rule, that is an alias for the aggregate rule. Other parts of the LRM make heavy use of these BNF "redirects". \$\endgroup\$ – Paebbels Feb 16 '18 at 18:45
  • \$\begingroup\$ The issue is basic operation. Assignment is not a function. That's spelled 'vice'. Annex I - aggregate: (B) A kind of target of a variable assignment statement or signal assignment statement assigning a composite value. The target is then said to be in the form of an aggregate. The standard is internally consistent. \$\endgroup\$ – user8352 Feb 16 '18 at 18:56
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Use the VHDL-2008 Library in ModelSim and your error is resolved. VHDL-93/2002 packages don't support aggregating vectors like the way you have expressed.

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    \$\begingroup\$ There isn't a comma operator. An aggregate is an expression, requires parentheses and includes one or more positional or named associations separated by commas. The new -2008 feature is that array aggregate association elements can be the type of the aggregate itself in addition to the aggregate element type. Prior revisions only support association elements of the aggregate element type. The type of the aggregate, it's element type and index type (for named association) are derived from context. Aggregation not concatenation. Your solution works, your explanation needs work. \$\endgroup\$ – user8352 Feb 8 '18 at 1:51

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