# Detrmining open loop gain of an amplifier in LT-spice using a transient simulation

Normally I would test an amplifier design in SPICE by using a method such as this:

Source: Analog tips open loop gain

I would run a .ac simulation and plot the result.

The amplifier I want to design is a chopper and so .ac sims do not work because I need to find the open loop gain at DC and my DC signal is being modulated. This restricts me to a .tran simulation.

How can I find a DC Open loop gain with a chopping amplifier in SPICE?

Right now I am using a sweeping b source as my input
V=1*sin(2 * pi * time * (1 + (2 * time))) and a transient simulation, and observing the output, it is not giving me the correct open loop gain close to DC.

This is the circuit of interest for simulation:

## Real Question

My real question is how do I find the open loop DC gain for this circuit (on paper and in spice)?

• Real answer: read the data sheet and design your end-goal circuit so that it does not rely on limitations in the open-loop gain!! I guess you'll respond with something interesting. That op-amp isn't a chopper BTW. – Andy aka Feb 8 '18 at 17:36
• Which op amp isn't a chopper ? The one at the top is not a chopper, that is to demonstrate how I would normally run an open loop simulation. The circuit at the bottom is a chopper, the input is 'chopped'. It doesn't function like modern amplifiers that negate both inputs at a switching frequency (it only has one input so it can't), but it still fits under the definition of a chopping amplifier. – Voltage Spike Feb 8 '18 at 17:55
• OK I see that but isn't the open loop gain calculateable from the op-amp data sheets? I'm struggling to see your problem. – Andy aka Feb 8 '18 at 17:58
• No, it goes deeper than that. Because the amps in the circuit are not in an open loop configuration. One way would be to calculate the transfer function of each piece (the first stage has an AC gain of 120dB or 10^5). The integrator, is well an integrator, with around 30dB to 40db at 0.01Hz and 0db at ~10Hz. – Voltage Spike Feb 8 '18 at 19:54
• @laptop2d Take a look inside LTspice's Educational/FRA folder. It has a few approaches to determining the loop gain in .TRAN, but it may require your simulation step to vary proportional to the measured frequency, for better resolution (shouldn't be hard to do it with .param's, but it will take a toll in time). You may need to run for more than 1 period for even better results. If you can, also check out Yahoo Group's Files/adventures_with_analog (IIRC), there's also a FRA in there that has similar goals, but it may only work with fixed sampling/switching frequency. – a concerned citizen Feb 9 '18 at 6:52

You could break apart into stages, and consider separately. First, the sampling is 925Hz, so anything beyond f0/2 is simply ignored. Second, there are two paths, dictated by each of the two pairs of switches, $Q$ and $\overline{Q}$.

The first stage would be the input RC, that's easy: fc~528kHz, consider flat. When $Q$ is active, input is active, else output is active; both go directly into the JFETs.

Then there's the differential nJFET together with A1 (they share the feedback network). Since the JFETs don't have capacitors around them, and since their parasitics would, most likely, go well beyond Nyquist, they're considered to have flat response, while the feedback network says you have a pole at $\frac{1}{2\pi 10\text{k}1\mu}\approx 16\text{Hz}$, with $Av=\frac{10\text{Meg}}{10\text{k}}=60\text{dB}$ and a zero at $\frac{1}{2\pi 10\text{Meg}1\mu}\approx 16\text{mHz}$, $Av=0\text{dB}$. Or write its transfer function as a shelf highpass (with R2=10Meg, R1=10k, C=1$\mu$):

$$H_1(s)=\frac{R_2}{R_1}\frac{s}{s+\frac{1}{R_1 C}}$$

There is at least a pole of the opamp which is beyond Nyquist, ignored.

The last stage is the integrator plus or minus the 1$\mu$F cap + switches. Their RDSon is considered too low compared to RDSoff. If $Q$, A2`'s input is grounded, its output will be the discharge of the feedback cap. If $\overline{Q}$, input is a passive highpass with C and RDSon, terminated with RDSoff which is, normally, much higher than the 240k, thus the output will be influenced by the integrator's input, which will also change the overall transfer function. At this point, I call LTspice to help and it turns out that the relevant transfer function is that of a highpass with fc well below 1mHz (~159$\mu$Hz, considering RDSoff=1G$\Omega$), together with a shelf lowpass with only the pole being below Nyquist, at ~325Hz (quite close to 462.5Hz), so you could write:

$$H_2(s)=\frac{s}{s+\frac{1}{R_{DSoff}C}}\frac{\frac{1}{R_1 C}}{s+\frac{1}{R_1 C}}$$

The overall open loop gain should be $H_1(s)H_2(s)$, depending on which path is active, $Q$, or $\overline{Q}$.

Closed loop voltage gain= Av=R2/R1 So change Acl=from 1e3 to 1e? and compare offset error reduction to obtain DC gain. Inject a DC input offset error if there isn't enough.

We expect DC offset error to be reduced by feedback Aol/Av, so raising Av significantly should increase offset error, thus Aol = Av*Vo offset