I have (i've hope not silly) question about types control in vhdl.

type data_t is record -- 16 bytes + 1 bit
    order       : std_ulogic_vector(7 downto 0);
    data        : std_ulogic_vector(111 downto 0); --14 bytes data
    data_en     : std_ulogic;
    card_addr   : std_ulogic_vector(7 downto 0);
end record data_t;

type order_respond_t is record -- 16 bytes + 1 bit
    order       : std_ulogic_vector(7 downto 0);
    timestamp   : std_ulogic_vector(15 downto 0);
    data        : std_ulogic_vector(95 downto 0);
    data_en     : std_ulogic;
    card_addr   : std_ulogic_vector(7 downto 0);
end record order_respond_t;

Previously I was working as embedded programer so I am curious how it is working with vhdl. The records have exactly the same size but different structure inside. Can I do something like this ?:

signal_order_respond_t <= signal_data_t;

In C I can assign two different structures to each other using pointer (so I can map data from one structure to different one (let's skip if it is useful or not at this moment).

Is it possible to do it in VHDL, is it right according to good practices of vhdl coding ?

  • 1
    \$\begingroup\$ stackoverflow.com/questions/13422993/… \$\endgroup\$ Commented Feb 9, 2018 at 16:58
  • 3
    \$\begingroup\$ Not in that way as VHDL does strict type checking. As they are non-standard types you have to write a conversion function. If you don't use it often you might save time and just assign them one-by-one. \$\endgroup\$
    – Oldfart
    Commented Feb 9, 2018 at 17:11
  • 1
    \$\begingroup\$ A type is characterized by a set of values and a set of operations (IEEE Std 1076-2008 5.1 Types). An object of a composite type represents a collection of objects, one for each element of the composite object (5.3). A record type is a composite type, objects of which consist of named elements (5.3.3). Record types are not compatible (9.3.6 Type conversions). Think trees with named element of potentially different types, not abutting linear arrays of subelements of the same enumerated character type. Strong typing implies objects are more than named references to underlying host storage. \$\endgroup\$
    – user8352
    Commented Feb 9, 2018 at 22:57

2 Answers 2


VHDL is strongly typed so what you request is not possible with some conversion functions. I would typically make some conversion functions that encode the record to a slv, and one that decodes from a slv to a record. With these functions something like the following is possible:

signal data : data_t;
signal order_respond : order_respond_t;
order_respond <= decode(encode(data));

Here's what the conversion code looks like. Realize with some helpers this can be simplified a bit as well.

subtype common_t is std_logic_vector(128 downto 0);
function encode(d : data_t) return common_t is
  variable comm : common_t;
  comm(7 downto 0)               := d.order;
  comm(111+8 downto 8);          := d.data;
  comm(112+8);                   := d.data_en;
  comm(112+8+1+7 downto 112+8+1) := d.card_addr;
  return comm;
end encode;

function decode(comm : common_t) return order_respond_t is
  variable order_resp : order_respond_t;
  order_resp.order     := comm(7 downto 0);             
  order_resp.timestamp := comm(8+15 downto 8);         
  order_resp.data      := comm(8+16+95 downto 8+16);                  
  order_resp.data_en   := comm(8+16+96);
  order_resp.card_addr := comm(8+16+96+7 downto 8+16+96+1)
  return d;
end decode;

Your question's a little confusing so let's see if this addresses it. Although you ask about 'type control', you show record types and your question seems to be about record types in particular. So I'll stick to that...

In VHDL, a record type is simply a convenient bundling together of a set of signals. As VHDL is a descriptor language, not a procedural programming language, it's more closely connected to a schematic.

In your record type, these signals are not having storage (memory) allocated to them. The signal assignments describe electrical connections between logic gates under specified conditions. These conditions may be explicit, such as with concurrent assignments, or implied, such as in a conditional process.

Since they're not being stored, you can't 'find them' using a pointer. Incidentally, you can't in Ada either, the procedural programming language that VHDL derives much syntax from.

In simpler terms, if you can see signals as wires* then just see record types as bundles of wires*.

(* I know these wires are often logic gate/register outputs but you get the idea)


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