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I have a 4 layer(Top-MID1-MID2-Bottom) PCB with VIA drill pairs as shown in the figure.

enter image description here IS it possible to manufacture a PCB like this?

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  • \$\begingroup\$ As per rules is it ok to make drill pairs like this? \$\endgroup\$ – litun bls Feb 10 '18 at 8:15
  • \$\begingroup\$ stopping the drill in the thin dielectric layers seems real tricky, \$\endgroup\$ – Jasen Feb 10 '18 at 10:53
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Ask your assembly house what is possible.

However, even if they can do it, it will be at a massive premium to the point that I would bet that HDI stacked microvia with a load more layers would be cheaper.

The issue is that you would need each layer to be drilled independently, and then lined up, they will get lots of duds and it will be a hugely more expensive and time consuming process then say a 8 layer simple or even an 8 layer with one or two layers of stacked microvia (Which is a standard process).

The mix of blind and buried is what makes it a real pain, but blind L1-L2 AND L1-L3 is a pain in the toot, could you not simply use L1-L3 and deal with the resulting stub?

This is however a question for your board house, capabilities vary widely.

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    \$\begingroup\$ Thanks! I am changing all blind vias and buried vias to through-hole vias. I think it will be cheaper. \$\endgroup\$ – litun bls Feb 10 '18 at 10:09
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    \$\begingroup\$ It will be very much cheaper, even if you have to go to 8 layers, blind and buried are expensive in small quantities and are almost always overkill on a 4 layer board. \$\endgroup\$ – Dan Mills Feb 10 '18 at 11:03
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No, it isn't possible.1

Each "drill-pair" used to create a via involves both drilling and plating. Once a particular pair has been processed, it is not possible to separate the layers to create unrelated pairs. You can only add one or more layers and then do any additional drilling through the resulting stack.

For example, in a 4-layer board you can have "blind vias" (top layer to mid1 and mid2 to bottom layer) by drilling and plating two two-sided boards independently. But the only thing you can do after that is laminate the two boards together with a layer of prepreg and drill/plate any remaining holes through the entire stack.

In a different scenario, you could have "buried vias" (mid1 to mid2) by drilling and plating a two-sided board. Then you could have blind vias to either the top layer or the bottom layer (but NOT both) by adding one-sided boards one at a time to the stack.

Either way, having three separate sets of drilling and plating operations instead of just one is what makes this so much more expensive for the fab house.

The only way to have both buried vias AND blind vias from both sides is to have a minimum of six layers — for example, three two-sided boards that are drilled independently and then laminated together with prepreg. Or two 3-layer stacks (2-sided + 1-sided) that get laminated together as the last step.


1After further research, that may be too strong a statement. I looked up the Eagle documentation on this, which seems to indicate that one-sided holes are possible — I was assuming that all holes had to be through holes in whatever portion of the stackup you're working with at the moment.

This means that you could indeed have all six possible kinds of vias in a 4-layer board. You would start with a 2-sided board for the inner layers, and do the buried vias in it. Then you would add the two 1-sided outer layers. The resulting stack would have to be drilled from both sides to two different depths for the four types of blind vias, and then one more time for the through vias before the final plating operation.

Depending on how you count, this would be a total of 6 separate drilling steps and 2 plating steps.

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  • \$\begingroup\$ It depends on who you use as much as anything. I would for example suspect that Wurth could do it, at a massive premium, while cheap far eastern PCB place, not so likely. That said with only 4 layers in play it is almost certainly massive overkill, just add another few layers or go HDI it will be far cheaper. \$\endgroup\$ – Dan Mills Feb 10 '18 at 22:50
  • \$\begingroup\$ Please let me know any web link or documents for IPC standards about layers, VIAs, track size and clearance rules \$\endgroup\$ – litun bls Feb 12 '18 at 9:57

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