Design an instruction using Thumb-2

Question

I'm studying the Cortex-M3 of ARM. The problem statement reads:

We're going to use a Harvard architecture with the following addressing capabilities: 32M words of code and 16-bit data words. The architecture can only address full words. The CPU has 16 internal general purpose registers and a Load & Store structure. With this information:

Design the coding of each group of instructions, minimizing as much as possible the instruction size. The instruction size shall be a multiple of the word size. The different groups are:

• 7 data transfer instruction, transferring data between memory and the internal registers, with direct addressing mode.

• 5 data transfer instructions, transferring data between memory and internal registers, using indexed addressing mode.

• 14 arithmetic/logic instructions to be executed between registers, being the destination register the same one as one of the input operands.

• 14 arithmetic/logic instructions to be executed between registers, being one of the operands provided by immediate addressing, and providing the results in the other source operand.

• 6 control instructions with inherent addressing mode.

• 7 conditional branches with PC-related addressing, being the relative addressing of plus/minus 1M word

This is the proposed solution that I don't undestand:

Direccionamiento directo: Direct addressing mode.

Desplazamiento: shifting.

What I do know is that the address bus of the program memory has to be of 25 bits, the address bus of the data memory has to be of 23 bits and the data bus of the data memory has to be of 16 bits. It is stated that the data bus of the program memory has to be of 31 bits but I do not know why since Thumb-2 is of 32 bit, or maybe I'm mixing things?

Answer 1

There isn't a single solution to such an assignment. The general idea is

• for each instruction group, determine how many bits are needed for the info within the group. For instance, 14 arithmetic 2-register instructions need a 4-bit code and two 4-bit register specifications, for a total of 12 bits.

• the remaining bits are used to distinguish between the groups. Use short encodings for groups that need most bits.

• place same type of bits fields in the same places, this eases decoding.

Answer 2

All of your inferences about bus sizes are wrong, the Cortex-M3 does demonstrate this. The much older architectures show that using a smaller bus size is however possible.

For direct PC branches, the jump size is limited. For indirect data or instruction operations, the address size is 32 bit (the register size). However, since the smallest quanta of instruction is 2 bytes, you only need 31 bits of instruction address (and byte access of instruction are not useful since you'd always need to do 2 at least).

Data immediate size is limited (per encoding IV), but you can calculate larger data values (and store them in registers), so you do need a 32 bit data value bus.

In your opcode design, the least flexible limitation is the size of the Rx fields (and of course the opcodes). The 'direct' fields can be shrunk to recover more space (just requiring more instructions to generate arbitrary constants). You can also play tricks like restricting the registers that certain (uncommon) operations are able to select. This allows you to overload the other register values for special instructions.