I'm studying the Cortex-M3 of ARM. The problem statement reads:
We're going to use a Harvard architecture with the following addressing capabilities: 32M words of code and 16-bit data words. The architecture can only address full words. The CPU has 16 internal general purpose registers and a Load & Store structure. With this information:
Design the coding of each group of instructions, minimizing as much as possible the instruction size. The instruction size shall be a multiple of the word size. The different groups are:
7 data transfer instruction, transferring data between memory and the internal registers, with direct addressing mode.
5 data transfer instructions, transferring data between memory and internal registers, using indexed addressing mode.
14 arithmetic/logic instructions to be executed between registers, being the destination register the same one as one of the input operands.
14 arithmetic/logic instructions to be executed between registers, being one of the operands provided by immediate addressing, and providing the results in the other source operand.
6 control instructions with inherent addressing mode.
7 conditional branches with PC-related addressing, being the relative addressing of plus/minus 1M word
Direccionamiento directo: Direct addressing mode.
What I do know is that the address bus of the program memory has to be of 25 bits, the address bus of the data memory has to be of 23 bits and the data bus of the data memory has to be of 16 bits. It is stated that the data bus of the program memory has to be of 31 bits but I do not know why since Thumb-2 is of 32 bit, or maybe I'm mixing things?