I am designing a system that can be expressed on an abstract schematic like this:
There is a main MCU that acts as I2C master and some slaves. Some of them are on the same PCB, but some are connected with cables on other PCB's. In case of Slave7 and Slave8, there is a "serial" connection: A long cable goes to the PCB4 from PCB1 and then from PCB4 to PCB5.
I am working in standard mode (100 kHz). Speed is not the case in here but reliability. This circuit seems to me to have a lot of capacitance because of many connected devices and long cables (from 1m to 2m). I am thinking of using I2C buffers, such as PCA9515A.
I consider few options:
Do not use buffers at all, maybe at this speed it is good enough with low resistance pull-ups?
Use only 1 buffer to divide the bus on 2 sides: On the 1st side: Master, Slave1, Slave2, Slave3 and Slave4. on the other: Slave5, 6, 7, 8.
Use many buffers (each PCB would have one). PCB4 would have 2, as it is "bridging" the bus to PCB5.
What do you think would be necessary? I understand that this is a function of bus capacitance and cables lengths, but I am looking for a scalable generic approach here. I would appreciate all help.
Sides notes: All devices are 3V3 logic, so no gain on making the signals amplitude higher. I was also wondering on converting the SDA bus signals to differential pair with dedicate IC's, but that seems to much, the cables are not that long.