I am trying to program this functionality onto a Xilinx FPGA; however, when I program it to do this, I get no output.
My situation is as follows:
I have 12 bits of data (in parallel): the first 6 bits are a sequence of 1s and 0s, and the remaining 6 are useful pieces of data. The goal is to send these 12 bits serially to a different FPGA (which will have a state machine programmed in order to decode the data).
The way I have been trying to send the data from the primary Xilinx FPGA is to have all twelve bits as inputs into a mux. The selector will be driven by a counter (going from 0-11) that is itself incremented by a clock pulse.
In theory, this doesn't sound too difficult for me... I have implemented it using Xilinx System Generator and, in simulation, it works fine. However, when I actually program the FPGA, I get no output! I have the FPGA hooked up to an oscilloscope and have verified that it worked. (The verification process involved comparing a 1MHz sine wave with 0 and pulsing whenever the sine wave is greater than 0; this worked.)
I am wondering if anything I am doing sounds wrong at first listen... Thanks a lot.