I am trying to program this functionality onto a Xilinx FPGA; however, when I program it to do this, I get no output.

My situation is as follows:

I have 12 bits of data (in parallel): the first 6 bits are a sequence of 1s and 0s, and the remaining 6 are useful pieces of data. The goal is to send these 12 bits serially to a different FPGA (which will have a state machine programmed in order to decode the data).

The way I have been trying to send the data from the primary Xilinx FPGA is to have all twelve bits as inputs into a mux. The selector will be driven by a counter (going from 0-11) that is itself incremented by a clock pulse.

In theory, this doesn't sound too difficult for me... I have implemented it using Xilinx System Generator and, in simulation, it works fine. However, when I actually program the FPGA, I get no output! I have the FPGA hooked up to an oscilloscope and have verified that it worked. (The verification process involved comparing a 1MHz sine wave with 0 and pulsing whenever the sine wave is greater than 0; this worked.)

I am wondering if anything I am doing sounds wrong at first listen... Thanks a lot.

  • \$\begingroup\$ Would you be so kind as to provide us with a diagram or a schematic. \$\endgroup\$ – user105652 Feb 11 '18 at 2:54
  • \$\begingroup\$ This is typically done with a shift register. Practically every class on digital logic has students build one, so there are gazillions of them floating around the net (just be careful--since it's a popular student project, there are probably at least a few that either don't work at all, or don't work particularly well). \$\endgroup\$ – Jerry Coffin Feb 11 '18 at 3:24
  • \$\begingroup\$ Thanks Jerry. Though I have looked into using a shift register, for some reason, that isn't working either. I am using OPAL-RT software, and all of this seems to work with an Artix 7 FPGA, but not theirs. \$\endgroup\$ – Lerbi Feb 11 '18 at 17:38

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