When the input is at 3.3 V, the R1/R2 voltage divider will only allow 350 mV base drive to the transistor. That will keep the transistor basically "off".
When the input is at 0 V, figure the B-E drop at 700 mV. That leaves 3.3 V across R2, so 3.3 mA will flow thru it. R1 will take 700 µV of that, leaving 2.6 mA to drive the transistor. If you use a transistor with a minimum gain of 50, for example, then it can support up to 130 mA of load current.
Since you didn't say anything about off-state leakage, on-state current requirement and allowable voltage drop, and current capability of the digital signal, this meets all your specs. Note also that the digital output will be driven from 4 V with 2 kΩ in series. But again, since you didn't say anything about the digital output, this is in spec.
Update to new specs
You now say the load might draw up to 500 mA. In that case, a single transistor won't do. You also probably care more about the voltage drop of the switch, although you still haven't said anything about that.
This should work nicely, and be able to switch well above 500 mA:
When the logic signal is high, Q2 is turned on. That causes the gate of Q1 to be driven low, turning it on.
Q1 is specified for 32 mΩ with 3.7 V gate drive, and 40 mΩ with 2.5 V gate drive. It will continue to work well as the battery gets depleted. Even at 40 mΩ, it will drop only 20 mV and dissipate only 10 mW.
Note that this version turns the load on when the digital signal is high. The first version, above, turns the load on when the digital signal is low.