555 timing capacitor discharge via threshold input

Question

The circuit below is the timing logic for the SC280 UV exposure unit. Based on my judgement the design of the circuit is poor - and I'm planning to replace it -, I'm posting my question only to learn something more about 555 timer circuits and debugging similar issues in the future.

^{simulate this circuit – Schematic created using CircuitLab}

The 555 is an NE555P, the UV exposure time is set with the R₁ potmeter from 0 to 5½ minutes, and the exposure is started with the SW₁ switch. The reason I checked the circuit is that the timer was inaccurate, the actual on-time was considerably less than the preset one (by up to a minute). As you can see the DISCHARGE and CONTROL pins are unconnected, even though they should be connected to C₂ and to ground via a capacitor respectively according to the 555 monostable circuit on Wikipedia.

My question is how C₂ discharges after the timer expires and if that way conforms to specification. Based on my measurement after pressing SW₁ until the preset time expires it charges up to 10V (= ⅔ * 15V), then it drops suddenly to about 1V and then discharges slowly towards 0V. I suppose this was the circuit designer's intention, but it still surprised me, given that the discharge pin is unconnected and that (as I imagined, but also based on the datasheet) both the TRIGGER and THRESHOLD pins should be high impedance inputs. After building this same circuit on breadboard, I measured the discharge current (up to 400μA) to be via the THRESHOLD pin, while I didn't measure any considerable current via the TRIGGER pin. Looking at the 555 internals this pin is connected to the base of a BJT (which in turn is part of the threshold comparator).

Does the above discharge current go via the BJT's base-emitter junction? Normally (when the 555 is permanently powered via its V_cc pin) the THRESHOLD pin doesn't draw any considerable amount of current even if the timer has expired, so I doubt that this high discharge current would be due to normal BJT BE current to keep the transistor open. Maybe it's via the BC junction, due to V_cc falling below the voltage level on the THRESHOLD pin?

Is there any problem in THRESHOLD and TRIGGER being above V_cc? At least according to this NE555 datasheet they shouldn't be above it.

Why would someone choose this design over the more obvious (and correct?) one where V_cc is always connected to 15V and C₂ is discharged via the DISCHARGE pin?

Answer 1

First I must say... YUCK.

When you close the switch it powers the 555 which in turn drives its output high, pulling in the relay to keep itself powered when you let go the button.

After the timeout the relay is released.

As you have discovered there is no actual discharge path for the capacitor. In reality what will happen is the capacitor will discharge through the power pin of the 555. Mostly through the three resistors that setup the reference levels, plus whatever quiescent current the 555 still draws with that voltage division.

That of course will result in a decay time longer than your set on-time. So the next time you trigger the circuit the delay will be significantly less if the cap has not had time to reach zero volts.

You can correct that a little by adding a low resistance discharge path, D2 and R3 down through the relay coil as shown below. I included D3 so the inductance of relay coil current does not pull a negative charge on the cap. Note: Using the discharge pin may not work, since the 555 is unpowered, the state of the discharge transistor is undefined.

^{simulate this circuit – Schematic created using CircuitLab}

You will still have a slight variation on second firing due to the diode drops though. Using shotky diodes would help, but watch out for the leakage currents on those.

Answer 2

My question is how C2 discharges after the timer expires and if that way conforms to specification.

In an ideal world it wouldn't, but capacitors got parasitic resistance in parallel with them, draining them. FYI: When you were measuring with whatever tool you were using, then you added another path for the current to flow => drained the capacitor even faster.

Specification... what specification? .. Doesn't matter which one I suppose, I wouldn't recommend depending on parasitic resistances that vary greatly from capacitor to capacitor, and depending on the input resistance of the internal op-amp.

I measured the discharge current (up to 400μA) to be via the THRESHOLD pin

Well the Threshold pin hooks up to an op-amp inside of the NE555, the op-amp is probably based off BJT's which has lower input impedance than CMOS based. So 400 µA is not impossible.

Is there any problem in THRESHOLD and TRIGGER being above Vcc? At least according to this NE555 datasheet they shouldn't be above it.

The datasheet is like the ten amendments or something along those lines. If the datasheet says so, then it is so. Going against the datasheet is like driving a car on the wrong side of the road. It might work for a while, but it is more probably that a failure will occur sooner than later.

Why would someone choose this design over the more obvious (and correct?) one where Vcc is always connected to 15V and C2 is discharged via the DISCHARGE pin?

The schematic in your question uses 0 current when it's off. Zero, zippo, nada. The "more obvious (and correct?)" solution uses around 300 µA all the time. Even when you are not using it.

Maybe the person who designed the schematic didn't know about the more obvious monostable 555. I don't think you did, because you used the person's schematic instead of the more obvious solution.

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When the voltage across C2 is above 1 V, then it is being discharged through it's parasitic parallel resistance and the threshold pin. After the 1 V it is being discharged only through the parasitic parallel resistance.