But how about designing a memory with different size cells? I can't find any material on it. Lets say in the above figure that i want to have also some cells of 256kx8bits. How will i proceed? Probably i will have to make some arrangements on the address length of the smaller chips. Also what decoder will i use for the row selection if for example i have 9 rows of chips? Or should i keep the number of rows in the form of 2^k?
Yes, it's perfectly possible to mix different size devices in the same address space. In fact, it's done all the time in microcontrollers where the size of ROM, RAM and various different memory-mapped I/O devices are often all quite different. You simply have to decide where each device is going to sit within your address space, give each device as many of the address lines as it needs to select between the different locations it holds and implement the appropriate address decoding with the remaining address lines.
Here's a simple example of how you might have four types of device taking up the whole of a 64K address space. The first decoder activates the 32K device when A15 is low; when A15 is high it activates the second decoder instead. This in turn activates the 16K device when A14 is low; when it's high it activates the final decoder instead, which uses A13 to determine which of the 8K devices to activate.
Obviously you can extend this to any number of memory devices and decoders. You may end up using 1 to 4 or 1 to 8 decoders instead, depending on device sizes, but there are various things you need to watch for. As you daisy-chain more decoders like this, the propagation delays will increase so you will need to ensure that the decoding happens quickly enough to allow your memory to run at the speed you want. It may be more practical to use some form of programmable logic to create the enable signals from the address lines; this may give you more design flexibilty as well.
The other thing you need to watch for as you add more devices is the loading on the address and data lines. Buffering the address lines is simple enough, but the data bus will need bidirectional buffering and that will require further logic to control.
Finally, it may not actually be necessary to decode the address space fully. If it's large enough compared to the size of your devices, and you don't need them to sit in contiguous address range, you can just break it down into blocks the same size as the largest device (or even larger) and use a single decoder with enough outputs. This is often more practical where a large number of I/O devices are combined that have only a small number of locations each; the addresses simply repeat one or more times within each division. Or you might decode some parts of the address space fully but only use partial deciding for others; it all depends on your application.
The other way to avoid having to decode the address space fully is to use a Memory Management Unit of some form that can map the physical addresses into a contiguous range of logical addresses.
to design the memory by using 1 type of memory cells
There're several advantages using only one type of memory blocks:
- you use same chips -> you buy more of same chips -> you get better price per chip;
- making contiguous RAM space with the same chips is easier and less costly in terms of glue logic.
Lets say in the above figure that i want to have also some cells of 256kx8bits.
So you have 256KB chips and 512KB chip, right? Then to "make up" one 512KB chip you use 2 256K chips. You "2-bit decoder" will become 3-bit decoder, you will need several OR gates to make chip select signals for 512KB chips.
Also what decoder will i use for the row selection if for example i have 9 rows of chips? Or should i keep the number of rows in the form of 2^k?
Row selection? You should talk about address and data bus width instead at the level of RAM chips. There're memories having 20 address bits, but actually having less RAM (e.g. IBM XT machine having 640KB of RAM); RAM can be in any processor addressable space, your task as designer is to ensure that processor can use that RAM as effective and efficient as possible.