For ADC/DACs, it is quite visual. Let's sample a signal (image from wikipedia):
The point at t=1 is on a high slew rate part of the waveform. Phase noise on your clock is a frequency domain concept, which corresponds to jitter in the time domain. Jitter adds time noise to the sampling instant.
Thus, here, our signal at t=1 has a voltage v and a slew rate dv/dt.
With "n" the amount of time-domain noise (jitter) the sampling instant is now t=1+n
Thus the value acquired is now v + n dv/dt
In other words sampling jitter introduces noise that is proportional to the product of jitter and slew rate. For fast ADCs with enough bits, the manufacturer will usually explain in the datasheet that the specs will only be met if the clock has less than a specific jitter.
divB posted this graph in the comments, it's quite explicit:
This is compounded by the fact that you can only get low phase noise crystal oscillators at "low" (by today's standards) frequencies. If you need 1GHz some PLL multiplication will be required, and as Tony Stewart mentions, this degrades phase noise. An intuitive explanation of this is that the PLL can't remove time-domain jitter in the original clock outside of its filter bandwidth, so this jitter is also present in the output, but it is larger relative to the shorter period of the higher frequency output signal. Expressed in phase noise terms, this gives the equation quoted by Tony.
Another one: here's your carrier. Ignore the legend, this is just an image from the web as an illustration.
Say you receive a signal, and multiply it with the carrier of frequency in order to demodulate it. The resulting spectrum is the convolution of the carrier spectrum and the received signal spectrum. This means the two phase noise peaks at +/- 100kHz from carrier will grab the noise at these frequencies and fold it back on top of the signal you actually want. This degrades SNR, especially in multiple close carrier modulations.