I need to do a tehnology mapping (group gates and flip flops) given a D ff and a MUX. Now I know what FPGAs mean and I understand I need to group them so that they "fit" in the given cell. But if I have only a D ff in my cell doesn't that mean I can group only the gates that are connected to the ff? A little help would be great cause I tried looking over some tutorials but didn't understand much.enter image description here


2 Answers 2


Try finding a truth table that describes the mux.

Then, split the table so that each of the subtables fit into the FPGA's tables, and connect the LEs so that the complete circuit works.

The flipflop can be mapped by simply configuring the output path of the last table combining the intermediate results to go through the register, while all the previous stages skip the register.

More details:

Your problem is a truth table with seven inputs, i.e. 128 entries. The technology mapping needs to reduce this to 16-entry tables with four inputs.

The simple approach is to generate eight tables that implement a part of the truth table each, then route the output of these tables to tables that implement a selection between two inputs:


simulate this circuit – Schematic created using CircuitLab

You will need seven of these to combine the outputs from the eight tables, and these will also need to be implemented using tables. Since you have only three inputs on these, you only populate half of the table and fix one of the selection inputs to zero.

There is probably also potential for optimization here, by looking for patterns in the truth table (when doing this by hand) or transforming the expression, but that is a lengthy topic that would now be counterproductive.

  • \$\begingroup\$ I know I'm asking for a lot now but could you please put a pic of how this type of problems can be solved?I had this in my previous exam and I didn't take it so I'm gonna retake it now but I have no clue how to finish this problem.I did the truth table but I get stuck so if you could help me with a pic I'd be extremelly grateful.I mention yet again its not a school assigment as it's something I've come across in my exam and really need to understand it :( \$\endgroup\$
    – Lola
    Feb 13, 2018 at 16:15
  • \$\begingroup\$ Thank you very much for the time given to write this answer it clarified a lot of things although I still have a hard time grouping them,maybe because I'm a noobie to this type of problems. \$\endgroup\$
    – Lola
    Feb 14, 2018 at 9:32

Normally FPGA cells have multiple outputs. One is from a register but there is also another which bypasses the register. Thus to make logic which can no fit in one cell you combine multiple cells but use the non-register output. Then in the last cell the output of the LUT goes to the register and you use the register output.

This seem to be a school assignment. In normal life you would use a programming language like Verilog to implement logic.

  • \$\begingroup\$ do you know any site where I could find more examples like this?Cause I'm still having trouble solving them and they weren't presented in depth at course \$\endgroup\$
    – Lola
    Feb 13, 2018 at 15:48
  • \$\begingroup\$ Sorry, no. I don't know where to find these. School is too many years ago for me. \$\endgroup\$
    – Oldfart
    Feb 13, 2018 at 17:17

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