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I've been trying to come up with a 6 layer PCB layout with microvias. But I cannot think of a cost optimized layer stack, because every manufacturer seems to tell me something different on their website. Since I'm quite confused I hope, someone can shed light on this.

Cost is always the driving factor. Thus, production steps have to be kept at a mimimum. My way of thinking went like this:

  1. We have 6 layers, so we have to press 2 times anyway.
  2. Let's name those layers: TO, TC, TI, BI, BC, BO (Top/Bottom Outer/Center/Inner)
  3. Drilling before the first production step seems to be unneccessary, so buried vias from TI to BI are not an option.
  4. Drilling is unneccessary for the inner layers. Microvias are laserdrilled and therefore much smaller and faster.
  5. This results in using microvias from:
    • TO to TC
    • TC to TI
    • BI to BC
    • BC to BO
  6. The final drilling and electroplating is done anyway, so Through Vias from TO to BO are okay too.

Is this the correct way of thinking and therefore the cost optimized layerstack for this kind of problem (given the given information and assuming standard production methods)? If not, which is?

If we take the cost of (1.) into account and not use all-through vias, how will this alter the cost structure?

Thinking about another possibility: Laser drilling from TO to TC AND TI. Is this a cost-viable option?

Proposed Layerstack Through Via Proposed Layerstack Buried Via Proposed Layerstack Microvia / Through Via

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  • \$\begingroup\$ The most cost effective way probably depends on the manufacturer's standard capabilities. Which is why they all tell you different things. \$\endgroup\$ – dim lost faith in SE Feb 13 '18 at 17:22
  • \$\begingroup\$ I have not yet needed to design a board with micro- or buried-vias before. Obviously it depends on the complexity of your board, but I just use vias top-to-bottom and connect them as needed on inner planes. If there's enough room on your board, this would be the simplest, cheapest option BY FAR \$\endgroup\$ – DerStrom8 Feb 13 '18 at 17:22
  • \$\begingroup\$ I need this connectivity on all layers. The strictest requirement is space, the lesser is cost. \$\endgroup\$ – einball Feb 13 '18 at 17:28
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    \$\begingroup\$ Cost optimisation is probably to restrict yourself to full through hole vias only - for 3 reasons : (a) single drilling stage, (b) simplified inter-layer alignment (c) simpler bare board testability. Unless your board density is high enough that you need blind vias to fit the available space. \$\endgroup\$ – Brian Drummond Feb 13 '18 at 17:38
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    \$\begingroup\$ If you must have the size, then you must have your \$\mu \$vias, though the only reason I've ever found the need for them was for fanning-out BGAs. Each manufacturer will have his own cost structure. You will simply need to do a partial/demo/example layout with each of your feasible layer stacks, detailed enough that you have realisitic via densities, and submit them all to all the vendors for quotes. \$\endgroup\$ – Neil_UK Feb 13 '18 at 17:44

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