4
\$\begingroup\$

I'm trying to add "optional" debugging test points to an existing, very dense 4 Layer PCB design (signal - GND - PWR - signal). I'd like to change the existing PCB as little as possible. My idea was to change the outline as shown below, adding a small debug area through a small neck (approx 5 mm tall by 1 mm wide) to the existing PCB: Block Diagram

This way, in an ideal world, when I get my PCBA's back from the manufacturer, and everything works, I can simply snap off the debug PCB and use the existing PCB as intended in end use. The current end-use mechanical dimensions don't allow for changing the PCB size. Then, before doing a bigger spin of PCBs, I delete the debug PCB, clean up the debug traces, and am ready to go.

Or, more realistically, if things aren't working as intended, I can attach logic/scope/meter probes easily to the traces via a 0.1" header (or similar) I've routed here. Figure out what went wrong, fix any mistakes and try again.

So the questions:

  1. Is this a reasonable approach, if trying to minimize the changes to the existing PCB? Other suggestions welcome.
  2. How can I minimize the chance that snapping the connection point will damage any existing PCB traces? Right now the route-keepin to board outline spacing is 0.25 mm = ~10 mil. I suppose increasing the width of the "part to snap" and aiming to snap closer Debug PCB should help, but other ideas welcome.
  3. I don't intend to extend L2 (GND) and L3 (PWR) to the Debug PCB, but should i still worry about them shorting at the "snap" area? Any ideas to mitigate this?
\$\endgroup\$
5
  • 3
    \$\begingroup\$ Sounds fine to me. Perhaps rather than snap off, five seconds with a "junior" hacksaw would reduce the chance of damage; 5 more seconds with a file to clean up. \$\endgroup\$ – user_1818839 Feb 15 '18 at 21:24
  • \$\begingroup\$ Yeah should be fine (I agree with @BrianDrummond - if you file the edge you won't short the planes or anything). An alternate approach is to use a high density connector to plug the "debug" board in - that way you can integrate it mechanically but still remove it and reconnect the debug board if something goes wrong. \$\endgroup\$ – Selvek Feb 15 '18 at 21:39
  • 5
    \$\begingroup\$ An alternative is test points and a DIY "pogo pin" fixture. No problems re-testing later on. electronics.stackexchange.com/questions/145468/… \$\endgroup\$ – user_1818839 Feb 15 '18 at 21:53
  • 1
    \$\begingroup\$ I'd look at other methods first (one I've been thinking of lately is edge fingers...) but if you want to do this make sure there's only one copper layer in the break region and make the traces weaker there, and fatter and/or via anchored to each side. Of course you'll need drill hits or something to make it break there. \$\endgroup\$ – Chris Stratton Feb 15 '18 at 22:06
  • \$\begingroup\$ Do you have blind/buried vias that make probing the PCB impossible? It seems odd to me that you are unable to probe signals on a 4-layer board (regardless of the density). And routing all the "debug" signals will introduce many stubs that will negatively impact any fast or noise-sensitive signals. \$\endgroup\$ – uint128_t Feb 16 '18 at 2:07
3
\$\begingroup\$

Don't make the middle part too small. PCBs are produced in a 'frame' and removing the PCB from the frame has the danger that the debug portion breaks off easily in the last stage of manufacturing. I would use two sots and leave a small connections at the outside and a bigger one, with routing in the middle. Below is a picture I took from the WWW of PCBS in a frame.

I would also make some solder points that you can reconnect the debugger later on.

enter image description here

\$\endgroup\$
3
\$\begingroup\$

It is not clear how big a run this PCB is or how complex the circuity is on the test part.

If it is a big run and the test part is fairly complex this is not a great idea in my opinion.

First you are paying to duplicate a circuit on each board that presumably you only need one or two of. Second if it fails, you need to check on each board if it is the main board that has the problem or the debug board. Also, as you have mentioned, you suffer from the risk of damaging the main board when you remove it.

You would be better to create a small run of a separate debug board which mates into a debug connector you add to the main board. You can then keep those debug boards as your gold standards.

If the debug board only contains traces... the connector alone, with an appropriate harness should be enough.

Later, you can unpopulate the connector from subsequent runs of the main board as a cost reduction.

However: if you have to run traces across the board so they can come out on the debug section, you may be adding more trouble than you are solving. Much better to have local test points and or test pins you can hook a scope onto where the trace is actually used.

\$\endgroup\$
3
  • \$\begingroup\$ This will be a small run, approx 10 pieces. The idea of the debug board isn't to duplicate the circuit, rather to expose more traces than I can get exposed to do any hands on debugging with the current circuitry. I do like the idea of instead using a connector and breaking out the connector's pins on a breadboard or similar, but not sure I have the space. Will have to investigate. Thanks Trevor. \$\endgroup\$ – Jim Feb 15 '18 at 22:48
  • \$\begingroup\$ @Jim just be wary of running long traces to it, especially any sensitive analog signals or clocks. Making your traces unnecessarily longer in the hope of making it easier to debug may cause the thing to fail all on it's own. \$\endgroup\$ – Trevor_G Feb 16 '18 at 14:01
  • \$\begingroup\$ good thinking. I do some clocks I'd like to have access to, but i'll keep their test points local. Thanks again! \$\endgroup\$ – Jim Feb 16 '18 at 14:19

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.