Critical damping of SMPS LC filter

I am designing a damping resistor [minimum load of SMPS] in parallel to output capacitor of LC filter.

SMPS specs:
1. Vout: 200 V
2. Iout [Max]: 2 A
3. PWM frequency: 50 kHz

Output filter specs:
1. L1: 680 uH
2. C1: 30 uF

Resistor value was calculated using R_damp = (Q*(Sqrt(L/C)))
With Q = 1, R_damp = 4.76 ohm.

This can set SMPS always in Over current protection state. Increasing the resistance makes the filter under damped. One solution I figured out was to place the R_damp in series with C_damp = (10*C). Here the Voltage across R_damp will not be Vout and hence lesser or no current as C_damp is open to DC voltage : Vout. So here the SMPS should not reach over current fault. Am I right or is there any way people go about damping SMPS LC filter? simulate this circuit – Schematic created using CircuitLab

• Congratulations. Most people don't think as hard as you do, and they get away with no explicit damping due to the load, resistance and core loss in the L, and ESR in the caps, taking the sting out of the worst overshoots. Putting Rdamp in series with C is the way to go. Try however putting estimates of L loss and C ESR into a simulator and see what you get, as it will reduce the amount of Rdamp you need. – Neil_UK Feb 16 '18 at 9:59
• Is this an extra ripple filter, or is that the buck converter output stage (and Vout is feedback to the controller)? – Jon Feb 16 '18 at 11:34
• Thanks Neil_UK. Was planning to consider that once I got this one cleared as it might have complicated the circuit. Any suggestion on how to model the inductor value changes with load currents changes? – renganathan b.s Feb 16 '18 at 12:58
• @Jon : it is output stage of buck converter. Yes, vout with resistor divider will be the feedback to the controller. – renganathan b.s Feb 16 '18 at 12:59
• @renganathanb.s is there a particular reason you want to damp the filter like this? In terms of output stability/overshoot you would also need to consider the feedback loop and the overall system transfer function. – Jon Feb 16 '18 at 21:02

Actually Dr. Middlebrook shown that an optimum $R_{damp}C_{damp}$ combination exists to bring $Q$ down to the value you want and minimize instability risks. You can take a look at the maths behind the determination of the optimum $RC$ here.

I realized that I first thought you wanted to damp a front-end EMI filter but it seems that you want to take care of the buck output $LC$ filter output impedance. I honestly do not see the point because damping naturally occurs with feedback as long as the selected crossover frequency offers sufficient gain at the $LC$ filter resonant frequency.

Anyway, the thing is to determine the peaking you have without damping and what your target is when damped. In this quick example, I considered that my design target was an arbitrarily-selected 10-$\Omega$ resistance for the maximum peaking once damping elements are installed. However, it is very likely that the final peaking is less than this value considering all dissipation factors in the filter - $r_L$, $r_C$, magnetic losses and so on which will naturally lower the $Q$ giving more margin at the end. The calculation of the damping elements gives $C_{damp}=36\mu F$ and $R_{damp}=6\;\Omega$. You can appreciate how far this is from the 300-$\mu F$ cap. you first computed.

The below Mathcad sheet shows you how the computation is done and how the resulting output impedance is damped for this 3rd-order filter (2nd-order plus another damping cap. is 3rd order).  In the above graph, you see the resulting output impedance plot whose peak is constrained to 20 dB$\Omega$, exactly our design target.

So in your case, you first need to determine the peak output impedance without damping and how low you want to lower the $Q$ once damping elements have been installed. Calculations are not trivial considering the 3rd-order filter, but the PPT given in the link contains all the elements you need.