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My understanding of an analog comparator is that you have a fixed reference voltage applied to one input and an AC signal to the other input, when the signal's voltage > reference voltage, the output of the comparator will be logic high, else logic low.

enter image description here

I was looking at the input stage of one of the MCU's analog comparators. Signal applied at AIN0, reference is applied at AIN1, pin5 toggles between Vcc and 0 to shift AIN1 by +- ~0.04V.

But what I don't understand is it has a 100k resistor (R2) connecting both inputs. What's the purpose of that? Wouldn't that make the reference vary as well?

Any suggestions are greatly appreciated, thanks.

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    \$\begingroup\$ DC reference because input has capacitive coupling only. \$\endgroup\$ – Martin Feb 16 '18 at 10:59
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    \$\begingroup\$ Why do you think the toggling of Port D.5 would shift AIN1 by +-0.4V? \$\endgroup\$ – Humpawumpa Feb 16 '18 at 11:05
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    \$\begingroup\$ I would guess that provides some hysteresis, but it looks like a lot less than 0.4V. \$\endgroup\$ – Finbarr Feb 16 '18 at 11:11
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    \$\begingroup\$ Then it's +/- 0.04V, not 0.4V. \$\endgroup\$ – Finbarr Feb 16 '18 at 11:14
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    \$\begingroup\$ Still sounds high though, I calculate it as just under +/- 25mV. Though that ignores the effect it has on the reference voltage, which would be irrelevant if it's done at high speed. \$\endgroup\$ – Finbarr Feb 16 '18 at 11:16
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The junction of R3 and R4 can be (should be) regarded as producing a fixed DC voltage of Vcc/2. C2 smooths any AC ripple on this voltage keeping it free from variations injected by the input signal via the 100 k resistor (R2).

But what I don't understand is it has a 100k resistor (R2) connecting both inputs. What's the purpose of that?

No, R2 just takes the Vcc/2 bias and applies that DC level to pin 7 so as to roughly centre pin 7 in the middle part of the range of the comparator's input.

R5 also couples Vcc/2 to pin 6 thus biasing pin 6 at Vcc/2 BUT pin 5 can modify that bias point via the 1 Mohms resistor R6.

I don't know where the circuit is used or for what but it looks like some kind of data decoder where the unknown data enters as the "signal input" and pin 5 is used (possibly at a high frequency toggle rate) to adjust the comparator trigger point.

If you can supply more details then I'm happy to fill in other gaps.

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  • \$\begingroup\$ I'm guessing it's used for frequency/period measurement :) \$\endgroup\$ – Finbarr Feb 16 '18 at 11:20
  • \$\begingroup\$ Excellent answer, thank you very much. It is indeed used for frequency measurement. Apparently the toggling is meant to increase noise immunity but I'm struggling to see how. \$\endgroup\$ – Shibalicious Feb 16 '18 at 11:23
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    \$\begingroup\$ It effectively filters out AC signals below the hysteresis level. \$\endgroup\$ – Finbarr Feb 16 '18 at 11:30
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    \$\begingroup\$ @Hypomania toggling may produce an effect called dithering and dithering can be used to produce greater resolution when converting from analogue to digital domains. For instance, in your circuit, if the input signal is very small you can avoid dead-band by dithering. \$\endgroup\$ – Andy aka Feb 16 '18 at 11:31
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    \$\begingroup\$ The raw signal may be superimposed on a DC level and therefore using C1 will get rid of the unwanted DC value. That is what I see as the importance of C1. If the DC level is stable and the overall signal amplitude is within the bounds of what the comparator can handle then you can DC couple. But you would need to remove R3 and R4 make R2 lower such as 10 kohm. You then have your pin 6 tracking the DC value of the raw signal. It's called a data slicer - see my answer here: electronics.stackexchange.com/questions/99049/… \$\endgroup\$ – Andy aka Feb 16 '18 at 11:48
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R3 and R4 (thank you for giving them designations) provide a mid-supply reference point. With 2 x 10k resistors the source impedance is 5k.

AIN0 has no DC path to ground due to the capacitor. We need to bias this to mid-supply so that the incoming AC signal swings around mid-supply. The 100k R2 provides the bias. C2 holds the reference steady and prevents it being disturbed significantly by the AC on the top end of R2. With 100k and 10u the RC time constant will be 1 s so you would need to compare this with the expected input signal to see if this is going to be a problem. (Presumably the designer has done this work and that there is not a problem.)


One question thought, why AC couple signal and then DC couple it, assuming that the signal's pk-pk is ~Vcc (I know I didn't mention this in the question, but in such case would that make AC coupling redundant?

The AC coupling removes any DC component and allows the coupled signal to be referenced to half-supply and it can now go positive and negative with respect to that. This means that it can accept a signal that oscillates around zero volts, or a negative or positive voltage.

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  • \$\begingroup\$ Thank you very much for your answer. One question thought, why AC couple signal and then DC couple it, assuming that the signal's pk-pk is ~Vcc (I know I didn't mention this in the question, but in such case would that make AC coupling redundant? \$\endgroup\$ – Shibalicious Feb 16 '18 at 11:26
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    \$\begingroup\$ You just want your AC input signal referenced to a given virtual ground and ignore any potential DC offset the signal might have. \$\endgroup\$ – Humpawumpa Feb 16 '18 at 12:02
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    \$\begingroup\$ @Hypomania: See the update. \$\endgroup\$ – Transistor Feb 16 '18 at 14:25

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