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Aerospace Vehicle Systems Institute (AVSI) has conducted research into this question.
"Accurate Quantitative Physics-of-Failure Approach to Integrated Circuit Reliability"
Their conclusions are based on physics and Root cause analysis especially since feature sizes have shrunk orders of magnitude over that last 30 years.
1) ElectroMigration (EM) (contamination of semiconductor from slow leakage of metallic ions)
2) Time Dependent Dielectric Breakdown (TDDB) or the slow tunnelling of a conductor path thru the oxide insulator from weak fields ( and gamma radiation )
3) Hot Carrier Injection (HCI), when a concentration of holes jumps a dielectric barrier in charge traps used by memory cells to permanently alter memory state caused by radiation gradually eroding the margin till failure.
4) Negative Bias Temperature Instability (NBTI) NBTI stresses, which shift PMOS transistor threshold voltages, have become more prominent as transistor geometries reach 90 nm and below and aggravated by static long duration charge traps enough to cause failure.
These FOUR REASONS above are the most common now with deep space IC's as well as consumer IC's. Space has more radiation and environmental stress factors. Moore's Law has also accelerated these new failure modes.
Historically, the most common generic reason for old technology IC's were limited in temperature range have to due with operating with packaging & environmental stress.
Thermal shock, condensing and rapid evaporation as well as analog effects of thermal drift Consumer IC are limited 0~85'C in plastic cases for this very reason. It is not a perfect seal and moisture ingress is possible. But even space hardened glass passivated ceramic IC's have thermal limits. In addition to the moisture issues stated below, read the most recent confirmed issues above.
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If there is enough moisture molecules over time and it freezes and cracks the substrate it fails.. If it is working ok in a frozen state with frozen molecules of moisture and then thaws and causes corrosion or leakage and fails. It's your fault. Some plastic seals are slightly better and self-heating prevents some from freezing below certain temps this also reduces migration of moisture.
At the high end , popcorm effect causes moisture to blow chips and Black epoxy grade has improved significantly over the last 40 years due to Sumitomo. Clear Epoxy is not as good and used in some LED cases or IR devices. So LED's must stay packed dry before soldering. Modern designs of large LED engines without the gold whisker wirebonds are rated to a certain RH @ Temp indefinitely, while the rest are a risk after a few days of open exposure to high RH. Really it's a valid risk and as bad as wounding them ESD, except it shears the gold wirebond.
This is why all space or military temp range parts tend to be ceramic with glass coating on leads and consumer parts are rated to 0'C.
Any exceptions such as Industrial and Military temp range are due to tighter specs needed for Military over a wider temp range than Industrial but they both function over a wide range just not guaranteed analog specs.
CMOS runs faster cold than hot. TTL funs faster hot than cold and junction temps drop to dissipate less heat. I have tested HDD 8" disk drives over a bag of dry ice < -40'C after an hour just for the military to prove it works, but no guarantees with condensation preventing head-crash.. ( the motor bearings squealed for a few seconds tho.... but passing 0'C from freezing going up... that's a humidity risk.
added journal references for proof.
The limiting reliability factor that affects the temperature of ALL integrated circuits ( especially large chips such as microcontrollers) is the mechanical packaging more than the function of the semiconductor. THere are hundreds of reliability articles to explain this. There are also articles to explain why there is a variance of low temperature limits. Some are de-rated from -40'C for good reason, and those extended from 0'C may be for bad reasons. Although not explicitly stated that profit is reason, junior engineers mis-apply HALT improperly to extend qualified ranges at risk from misunderstanding the chemical migration and structure stresses that exist. While wiser companies will re-derate with good reasons, which I will support with references below.
1. Hermetically sealed properties are not a digital phenomena.
It is analog and relates to the amount of ingress or moisture leakage atomically creaps into a mechanical package.
As stated in above link
"the internal outgassing may induce the formation of water droplet condensation, thus compromising the device performance and even- tually leading to device failure."
2." seals produced were hermetic initially, but tended to fail catas- trophically during prolonged soaking and temperature cycling in saline because of the difference in the CTE between the glass capsule wall (5.5 × 10−6/◦C) and the 90% Pt–10% Ir feedthrough (8.7 × 10–6/◦C). "
" From the nomograph in Fig. 6, it can be seen that at 1.0 atm and 0◦C, the moisture concentration needed for forming water droplets is 6,000 ppm. At levels below this percentage of water vapor, liquid drops will not be able to form. Hence, most materials and sealing processes are selected to keep the internal package environment at or below 5,000 ppm of moisture for the lifetime of the device." However contamination can alter this.
I could write a book on this subject, but then so many others have already, so I will merely reference some literature, which will prove my answer is valid.
Keywords with links
