Extract a motion filter using camera movement in number of pixel and angle, in VHDL or Verilog

Question

I have read some papers about the topic and searched some MATLAB algorithm. There is one called 'fspecial' in MATLAB. And it could return a Motion filter, when motion is given in number of pixel and angle. I have read 'fspecial' working principles and and it contains many MATLAB built-in function like max, mod, cos, sin, sign, fix, meshgrid, sqrt, abs, find. Is it difficult to implement this MATLAB code in VHDL to obtain a Motion -blur filter.

... This code is portion of 'fspecial' in MATLAB ******
case 'motion' % Motion filter uses bilinear interpolation

 len = max(1,p2);
 half = (len-1)/2;% rotate half length around center
 phi = mod(p3,180)/180*pi;

 cosphi = cos(phi);
 sinphi = sin(phi);
 xsign = sign(cosphi);
 linewdt = 1;

 % define mesh for the half matrix, eps takes care of the right size
 % for 0 & 90 rotation
 sx = fix(half*cosphi + linewdt*xsign - len*eps);
 sy = fix(half*sinphi + linewdt - len*eps);
 [x y] = meshgrid(0:xsign:sx, 0:sy);

 % define shortest distance from a pixel to the rotated line 
 dist2line = (y*cosphi-x*sinphi);% distance perpendicular to the line

 rad = sqrt(x.^2 + y.^2);
 % find points beyond the line's end-point but within the line width
 lastpix = find((rad >= half)&(abs(dist2line)<=linewdt));
 %distance to the line's end-point parallel to the line 
 x2lastpix = half - abs((x(lastpix) + dist2line(lastpix)*sinphi)/cosphi);

 dist2line(lastpix) = sqrt(dist2line(lastpix).^2 + x2lastpix.^2);
 dist2line = linewdt + eps - abs(dist2line);
 dist2line(dist2line<0) = 0;% zero out anything beyond line width

 % unfold half-matrix to the full size
 h = rot90(dist2line,2);
 h(end+(1:end)-1,end+(1:end)-1) = dist2line;
 h = h./(sum(h(:)) + eps*len*len);

 if cosphi>0,
   h = flipud(h);
 end

I wonder, whether I have in correct way to implement a motion filter in VHDL. Maybe there should be an effective way to this task? Or is there already implemented motion -filter in VHDL or Verilog ?

Thank you.

Answer 1

Implementing that function in Verilog or VHDL is far from trivial. Also what I gather this has to be calculated for each pixel. Thus it will need a s[censored]od amount if pipelining and/or parallel processing.

Then you still need a way of getting the pixels into and out of your FPGA. All and all a project which, I won't say can't be done, but I very much suspect is beyond your abilities.