In his chapter on CPU design, Edward Bosworth introduces the following three-bus architecture:

three bus CPU

One of the main design aims of this circuit is to be able to increment the program counter PC in a single clock cycle. According the the accompanying text, this is achieved by driving B1 from PC, B2 from the +1 constant register, asserting the add signal on the ALU and driving PC from B3:

PC <- PC+1: PC -> B1, 1 -> B2, add, B3 -> PC

The obvious question is then, how can the PC register drive B1 with one value while simultaneously loading another value from B3?

I can come up with two possible workarounds, but both have obvious issues.

  1. The transfers do not happen simultaneously. For example, B1 is driven on the rising edge, whereas the signal is loaded from B3 on the falling edge. But then, when we stop driving B1 the signal would vanish on B3 in the absence of another register in the path. If you do use an intermediate register somewhere (in the ALU?), you really are just doing two-cycle increment using half-cycle cycles.
  2. The PC register is actually two registers, one for output and one for input, that are not connected when the register is loading. But then you would need some sort of "equalization logic" that could turn out to be non-trivial.

So what is going on here?


1 Answer 1


Turns out I missed a crucial detail in the accompanying text, and the registers are indeed composed out of two (master-slave) sub-registers:

The Use of Master–Slave Registers

Note that the contents of the PC are incremented within the same clock pulse. As a direct consequence, the PC must be implemented as a master–slave flip–flop; one that responds to its input only during the positive phase of the clock. In the design of this computer, all registers in the CPU will be implemented as master–slave flip–flops.

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    \$\begingroup\$ Got to love Rubber Duck problem solving ;) \$\endgroup\$ Jul 13, 2012 at 14:17
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    \$\begingroup\$ @drxzl - Yes, it's EE that profits from it, and therefore it's good to post your answer. Always interesting for other users. You'll get the upvotes, but the 15 rep for accepting stays in the warehouse :-) \$\endgroup\$
    – stevenvh
    Jul 13, 2012 at 14:20
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    \$\begingroup\$ It's worthwhile to note that while edge-triggered flip flops are "the norm" today, that was not the case in decades past. Many processors like the venerable 6502 used two or more non-overlapping clock pulses to operate different parts of the logic; those pulses could either be generated off the edges of a reasonably-square clock (as was done with the 6502) or could be generated by subdividing a higher-frequency clock (as was done on the 8031). I believe many PIC processors still use such approaches. Some older processors used "dynamic logic" latches rather than conventional ones... \$\endgroup\$
    – supercat
    Jul 13, 2012 at 17:20
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    \$\begingroup\$ ...to further save circuitry (a "dynamic transparent latch" could be implemented with two active transistors and one passive pull-up, while a static one would likely require at least four transistors and two passive pull-ups). \$\endgroup\$
    – supercat
    Jul 13, 2012 at 17:21
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    \$\begingroup\$ @drxzcl: If one were designing a chip at the transistor level, one might be able to achieve some considerable savings in cost and/or power consumption by using things like transparent latches. On the other hand, it's much easier to reason about designs which use entirely edge-triggered latches all running off a common clock. There are times I find purely-synchronous designs to be a nuisance (e.g. the STM32LF series of microcontrollers allows one to keep a 32,768Hz crystal running while the processor is asleep, but its counters are all run synchronous to the main clock... \$\endgroup\$
    – supercat
    Jul 16, 2012 at 15:25

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