I'm developing a custom protocol processing device based on MCU. My protocol is somewhat similar to I2C and uses bit-banging instead of hardware implementation. I've done a prototype based on Atmega328P, mostly due to plenty of help online and cheap development boards. When everything started to work, I discovered that I'm not satisfied with the maximum speed of protocol processing logic. Even though most instructions are processed in 1T on Atmega328P, and it has a reasonably fast ISR latency (only 4T), the main problem is a lot of push/pop instructions are added to preserve/restore registers.
Now, I'm considering some other MCU architecture, which will allow me to run my code faster. I hope modern 8051 core based MCU might be an option.
EMF8 for example can run on 50-75MHz, same as ARM, can run 70% of instructions in 1T. Although, it will take 9T+9T to enter and exit ISR, I hope that it may not need to push/pop so many registers, as it can work with RAM directly, without mandatory use of registers (as in Cortex). For some reason
AT89 are not even listed on Microchip web site after take over of Atmel. There others available, but I don't know how they can be compared.
Cortex-M0(+) is another option, but there people on the internet complaining about large ISRs latency, even though according to ARM it should be streamlined and efficient. Although it will allow me to run code 3x times faster on 48MHz, it will most likely to suffer from the same issue as Atmega328P, as it had to push/pop lots of registers. I also don't think that I will benefit from 32 bit architecture, as my code doesn't use any math and mostly based on
I hope people have experience with new 8051s and can provide their opinion.
=== EDIT to provide more details ===
- The protocol is synchronous, it uses 2 pins: one for clock, one for data.
- ISR is on pin change, however with
AVRI can't have separate ISRs for clock and data, as both pins on the same port. I have more logic in ISR to identify which pin has changed.
- On 16MHz clocked
atmegaI'm having 10kbps (kilobit) with full logic in ISR and 50kbps with bare minimum. I established that 25us after pin toggle in master is sufficient for slave to process the change with bare minimum of logic. 10us is not enough, it starts missing clock.
- The code is implemented in pure C no ASM. All push/pops are inserted by
avr-gcc. I can see in decompile that all registers