Codec in 'master mode' require more than one external clock? (MCLK?) to drive I2S system timing to/from MCU slave?

Question

Does an audio codec in 'master mode' require more than the one clock line (MCLK?) to drive and time I2S data sync to MCU or FPGA slave?

I understand that the I2S proper consists of three lines - 'bit CLK', 'word CLK', and 'serial data'. Additionally, a 'MCLK' is used for delta-sigmoid and filtering. I understand that these signals should all have the same clock 'domain', as in clcok timing derived by division of the MCLK as required, based on bit depth (data length) and if 1 or two channels.

Does a suitable codec in master mode take care of all of these clocks? (Or do we need to generate two or all three I2S clocks?)

There are also the I2C control lines to read and write codec registers. Do these I2C lines need to be part of the same clocking domain as the I2S system is in? Thanks.

Oh, and finally, i understand that I2C register read/writes called from MCU/FPGA do not need to be in the same clocking domain (or same frequency) as the I2S signals - Is this understanding correct? (This application will wait for data available at port, then read/write audio to codec, then process the new data point, then wait for next word to be ready at codec to repeat the process.)

Answer 1

Generating the other clocks is the whole point of master mode, so that is indeed what an I²S chip is likely to be doing. But if you want to be sure, read the datasheet of your codec. For example, the CS4245 one says:

4.2.3 Master Mode

As a clock master, LRCK and SCLK will operate as outputs. The two serial ports may be independently placed into Master or Slave mode. Each LRCK and SCLK is internally derived from its respective MCLK with LRCK equal to Fs and SCLK equal to 64 x Fs.

The I²C bus has its own clock line, and the I²C protocol allows both master and slave to delay clock cycles, so it's impossible to demand that it be synchronous to anything else. But again, read the datasheet, which will say something like this:

4.12 Control Port Description and Timing

[…] The operation of the control port may be completely asynchronous with respect to the audio sample rates.

Some codecs might require that a valid master clock is present for the I²C to work.