Does an audio codec in master mode require more than one clock line (MCLK) to drive and time I2S data sync to MCU or FPGA slave?
I understand that I2S proper consists of three lines - 'bit CLK', 'word CLK', and 'serial data'. Additionally, a 'MCLK' is used for delta-sigmoid and filtering.
I understand that these signals should all have the same clock 'domain', as in clcok timing derived by division of the MCLK as required, based on bit depth (data length) and if 1 or two channels. Does a suitable codec in master mode take care of all of these clocks, or do we need to generate two or all three I2S clocks?
There are also the I2C control lines to read and write codec registers. Do these I2C lines need to be part of the same clocking domain as the I2S system is in?
Oh, and finally, I understand that I2C register read/writes called from the MCU/FPGA do not need to be in the same clocking domain (or same frequency) as the I2S signals. Is this understanding correct?
(This application will wait for data available at thd port, then read/write audio to the codec, then process the new data point, then wait for the next word to be ready at the codec to repeat the process.)