Comment from http://electronics.stackexchange.com/questions/356185/nand-flash-retention-using-usb-charger/356190?noredirect=1#comment855287_356190 claims that reading from flash storage is no lossless operation, so they get refreshed by the flash controller on spare time.

These filesystems do not use journaling, so ejecting the card or losing power during a write can corrupt it. Even with journaling, power loss during writes on flash is a touchy issue... you might lose more than the data that is being written, and it can spread to adjacent blocks too. A simple write may cause the controller to decide to move data around, etc... https://cseweb.ucsd.edu/~swanson/papers/DAC2011PowerCut.pdf


Doesn't repeated refreshing wear out these floating-gate transistors?

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    \$\begingroup\$ I am very curious to know how you interpreted that comment that way. \$\endgroup\$ Commented Feb 18, 2018 at 17:38
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    \$\begingroup\$ Can you edit a copy of the comment into your question for the readers. \$\endgroup\$
    – TonyM
    Commented Feb 18, 2018 at 17:39
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    \$\begingroup\$ Restored the original asker's emphasis on the actual question, since people have been answering the title and overlooking the question bolded by the asker. \$\endgroup\$ Commented Feb 18, 2018 at 18:59
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    \$\begingroup\$ @ChrisStratton, in fairness to those answerers, the OP shouldn't have a question in the title that's different to the question they're asking. Bold text doesn't fix that, correct wording does. \$\endgroup\$
    – TonyM
    Commented Feb 22, 2018 at 22:33

2 Answers 2


No, reading does not wear out flash memory. Look at any flash memory datasheet. It is erasing and writing that damage the oxide insulation between the gates and the FET bodies. Reading does not.

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    \$\begingroup\$ This may be true for low density devices likely to be used in custom designs. But for the cutting edge parts in modern high end computer SSD' passive retention times are apparently short enough that the controller must do active refreshes. The asker's question ultimately boils down to asking if these automatic active refreshes count against the overall write life. They may also be asking if reading accelerates the refresh need or if it is only driven by temperature - or they may not really be aware of that aspect. \$\endgroup\$ Commented Feb 18, 2018 at 18:38

Activating the read lines in a Flash module can result in lowering the number of electrons stored in a cell.
But the answer is much more complex.
The stored charge will leak away with time/temperature, so a cell with few electrons (perhaps only 100 or so) will eventually lose electrons and be sensed as a zero when it should be a one. To alleviate this different controllers will alter the read voltage threshold and/or read/error correct - erase and refresh the data. Flash memory may be single or MLC, and in the case of MLC the leakage problem and read disturb is accentuated.

This paper is a good explanation of the complexity involved.

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    \$\begingroup\$ I took the liberty of copying an very important line from that report. Retention errors, caused by charge leakage over time after a flash cell is programmed, are the dominant source of flash memory errors. \$\endgroup\$
    – user105652
    Commented Feb 18, 2018 at 23:08
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    \$\begingroup\$ users.ece.cmu.edu/~omutlu/pub/… \$\endgroup\$ Commented Feb 19, 2018 at 11:14

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