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I have read on several places that NOR flash have lower latency when it comes to reading compared to NAND version but I don't understand is this architectural consequence or due to, often different, interfaces.

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  • \$\begingroup\$ Both. NOR flash can be addressed and read like static RAM, as individual bytes or words. NAND flash is accessed a bit like hard disks, as full sectors. The difference is due to the way storage cells are interconnected. Since their invention, NOR and NAND have been optimised for different purposes. \$\endgroup\$
    – TEMLIB
    Feb 18 '18 at 21:09
  • \$\begingroup\$ This has been asked before, pretty much exactly like this, but I'm on mobile and have a hard time searching. \$\endgroup\$ Feb 18 '18 at 21:10
  • \$\begingroup\$ @TEMLIB But how architecture of NAND makes it slower? Only thing that comes to my mind is that due to longer signal path from bit line to ground it may take longer reach stable state when reading bit value? \$\endgroup\$
    – anaj
    Feb 19 '18 at 0:23
  • \$\begingroup\$ @MarcusMüller I would appreciate it if you could post link, if you manage to find it. \$\endgroup\$
    – anaj
    Feb 19 '18 at 0:27
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    \$\begingroup\$ electronics.stackexchange.com/questions/342583/… \$\endgroup\$
    – DiBosco
    Feb 19 '18 at 14:40
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The difference in read speeds between NOR (few nanoseconds) and NAND (microseconds) is due to the difference in architecture of read logic. just consider the read operation of just one bit (the arrangement of bit and word lines in NOR vs. NAND is a different topic). The read of each memory cell is done by applying convenient voltages to its terminals and measuring the current that flows into the cell. NOR and NAND memories measure this current in different ways:

NOR:

The read operation is done differentially. The desired cell is biased and at the same time a 'reference cell' is biased with the same voltage. the current in both is measured and then compared. The biasing (both measuring and reference cell), equalizing, and current comparison takes around nanoseconds in modern flash memories.

NAND

In NAND the cells are connected in series and therefore the current to be read/sense is 200–300 nA. This makes the differential sense method difficult; instead, charge integration is used. The bitline is charged by a defined amount and then checked whether it gets discharged (indicating that bit is erased) or not (no discharge means the cell/bit is not sinking and therefore set). The setup time to precharge the bitline (2-6 µs), then to let it discharge and evaluation (5-10 µs), is what takes time and makes the NAND read operation slow.

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