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VHDL is type-safe, thus how is it that I am able to use a std_logic_vector signal and port map it to a entity port that is of type signed?

Shouldn't it require some sort of "qualification" or "casting"?

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2
  • 1
    \$\begingroup\$ What kind of tool are you using? In Vivado, it is marked as an error: "[Synth 8-2778] type error near input ; expected type signed"... \$\endgroup\$
    – gstorto
    Commented Feb 18, 2018 at 22:15
  • \$\begingroup\$ As @gstorto asks, what software tool is letting you do this? \$\endgroup\$
    – TonyM
    Commented Feb 18, 2018 at 22:44

2 Answers 2

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You can use a type conversion in an association list e.g. in a port map.

Depending on the (port) direction, you need to specify the conversion either on the formal (output), actual (input) or both sides (inout).

port map (
  myUnsigned                  => unsigned(mySLV1),  -- input  (in)
  std_logic_vector(mySigned1) => mySLV2,            -- output (out)
  std_logic_vector(mySigned2) => signed(mySLV3)     -- bidirectional (inout)
);
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It is actually not allowed:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

-- ============================================================================ --
-- Entity declaration                                                           --
-- ============================================================================ --
entity first is
    port
    (
        input  : in  std_logic_vector(7 downto 0);
        output : out std_logic_vector(7 downto 0)
    );
end entity first;

architecture rtl of first is
-- ============================================================================ --
-- Signal declaration                                                           --
-- ============================================================================ --

-- ============================================================================ --
-- Code starts                                                                  --
-- ============================================================================ --
begin
  second_inst : entity work.second
    port map (
      input => input,
      output => output
    );
end architecture rtl;

#

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

-- ============================================================================ --
-- Entity declaration                                                           --
-- ============================================================================ --
entity second is
    port
    (
        input  : in  signed(7 downto 0);
        output : out signed(7 downto 0)
    );
end entity second;

architecture rtl of second is
-- ============================================================================ --
-- Signal declaration                                                           --
-- ============================================================================ --

-- ============================================================================ --
-- Code starts                                                                  --
-- ============================================================================ --
begin
  output <= input;
end architecture rtl;

The error is detected by Vivado, and I am pretty sure the same should happen with Quartus:

ERROR: [Synth 8-2778] type error near input ; expected type signed [first.vhd:27]
ERROR: [Synth 8-2778] type error near output ; expected type signed [first.vhd:28]
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3
  • \$\begingroup\$ It's possible. As the OP asked, a type cast - VHDL calls it type conversion - is required. \$\endgroup\$
    – Paebbels
    Commented Feb 18, 2018 at 23:16
  • \$\begingroup\$ @Paebbels If you are type casting to unsigned/signed, you are not filling a std_logic_vector to the submodule. It is the same thing as saying that when you are casting a std_logic_vector to unsigned and applying an increment, you are doing arithmetical operations with a std_logic_vector, which is not true. \$\endgroup\$
    – gstorto
    Commented Feb 18, 2018 at 23:23
  • \$\begingroup\$ The reason for your errors is that the two ports named inputs have different base types. One has a base type of std_ulogic_vector, the other unresolved_sign (or signed for pre -2008). std_logic_vector and signed can undergo explicit type conversion to the other because they have the closely related element types (both have an element base type of std_ulogic) and dimensionality. \$\endgroup\$
    – user8352
    Commented Feb 20, 2018 at 5:25

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