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I'm trying to make a controller for the MAX31855 thermocouple IC. My FPGA works at 50 MHz and this IC works at 5 MHz, so I'm using a frequency divider to get the 5 MHz clock signal.

Now the IC is sending to the FPGA its 32 data bits, at 1 bit per clock cycle. So I don't know exactly how to sample this (5 MHz) bit stream with a 50 Mhz clock signal.

I'm also thinking in metastability problems.

Any ideas?

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  • \$\begingroup\$ What kind of interface does your IC have? Usually this sounds like a non issue due to cleanly defined interfaces and existing IP /hardware transceivers. \$\endgroup\$ Feb 18, 2018 at 23:46
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    \$\begingroup\$ clock enable circuit. Count to from 0 to 9, and your allow your circuit to be clocked whenever the counter = 0. You can sync the clock by resetting the counter to 5 each time you detect a transition in the incoming data. (that puts your enabled clock edge right in the centre of the incoming data stream). I can turn this into a full answer in the morning (its midnight here). \$\endgroup\$ Feb 18, 2018 at 23:49
  • \$\begingroup\$ If your FPGA can output 50 MHZ or an even fraction of it you can use flip-flops to sync the 5 MHZ clock so you have no metastable jitter. \$\endgroup\$
    – user105652
    Feb 19, 2018 at 0:27
  • \$\begingroup\$ Tom Carpenter. Can you please turn that into a full answer? Thanks in advance! \$\endgroup\$ Feb 19, 2018 at 13:57
  • \$\begingroup\$ when you say "You can sync the clock by resetting the counter to 5", you mean, just the first time (for the first bit I mean), right? like in RS-232 \$\endgroup\$ Mar 10, 2018 at 19:51

1 Answer 1

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You say you have a frequency divider. But that is just the beginning. Indeed you have to add a synchroniser for the serial input. I looked at the datasheet and you need an SPI interface without the transmit part. That means you also need a chip select, serial/parallel converter, . I am not going to write that for you (After all that is what I earn my money with) so I am going to give you the most important snippets:

  always @(posedge clk or negedge reset_n)
   begin
      if (!reset_n)
      begin
         ser_in_meta <= 1'b0;
         ser_in_sync <= 1'b0;     
      end
      else
      begin
         // Sync input on system clock 
         ser_in_meta <= ser_in;
         ser_in_sync <= ser_in_meta;
      end
   end

         // Divide by 10 counter
         if (clock_div==4'd9)
            clock_div <= 4'd0;
         else
            clock_div <= clock_div + 4'd1;

        // Symmetrical 1/10 system clock
        if (clock_div==4'd0)
           ser_clk <= 1'b0;
        else
           if (clock_div==4'd4)
              ser_clk <= 1'b1;

        if (sample)
        begin
           bit_count <= bit_count + 5'h1;
           // Receive: MS bit arrives first 
           shift_in  <= {shift_in[30:0],ser_in_sync};                    
        end        

   // pick up the data just before the falling clock edge 
   assign sample  = (clock_div==4'd9);

The Maxim datasheet says the data is changing max 40ns after the falling clock edge. So pick it up just before.

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  • \$\begingroup\$ Thank you sir. What's the meaning/purpose of ser_in_meta, ser_in_sync and ser_clk? \$\endgroup\$ Feb 20, 2018 at 22:22
  • \$\begingroup\$ ser_in_meta and ..sync are what gets the asynchronous ser_in signal in phase with your system clock. I takes care of what you call "the metastability problem". The MAX31855 needs a clock which we generate here named "ser_clk". \$\endgroup\$
    – Oldfart
    Feb 20, 2018 at 23:12

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