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I would like to open and close a shutter (acousto-optic modulator) really fast. Really fast in this case means 2 MHz. However, the shutter should not be modulated periodically, e.g. with constant frequency. The shutter shall open, when an analog input signal Uin is above a certain threshold U1 and close again above another threshold U2.

Furthermore, the voltages U1 and U2 are provided digitally as 16 bit numbers. Both are not static, however. They will change in the worst case with a frequency of 1 MHz.

An added bonus would be, if the actual level of Uout does not have to be binary but could also be modulated with 1 MHz.

I tried to sketch a schematic for this:

schematic

simulate this circuit – Schematic created using CircuitLab

So obviously I thought to solve this problem using either a window-comparator or a FPGA. The latter one would give me more flexibility on future changes. Looking a bit on the National Instruments website, I did not find a fast enough FPGA (actually the DA/AD outputs/inputs are not fast enough).

The problem itself seems very basic to me. Am I overlooking an obvious implementation?

Thanks

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  • \$\begingroup\$ how much jitter is acceptable? is the difference between U1 and U2 fixed or variable? \$\endgroup\$ – Jasen Feb 19 '18 at 9:24
  • \$\begingroup\$ How accurate do you really have to take your comparison? You say your thresholds have 16 bit, but that's a) a lot and b) not necessarily the precision that your application needs... And: what's the Max rate of change of U_in? \$\endgroup\$ – Marcus Müller Feb 19 '18 at 9:27
  • \$\begingroup\$ @Jasen the difference between U1 and U2 is variable. But it will be an integer multiple of a smallest difference (obviously, since the voltages come in encoded 16 bit). So in practice I could also "chop" the intervals such that the difference between U1 and U2 becomes fixed, namely "1bit". \$\endgroup\$ – AnatraIlDuck Feb 19 '18 at 9:33
  • \$\begingroup\$ @Jasen the actually needed resolution would be 14 bit. So there is a bit of room for jitter. By the way, the Uin comes with +-10V. 16 Bit therefore corresponds to 0.3mV and acceptable jitter is 1.2mV. \$\endgroup\$ – AnatraIlDuck Feb 19 '18 at 9:39
  • \$\begingroup\$ @MarcusMüller I hope the previous reply also answers your first question (necessary resolution is at least 14 Bit). U_in is an analog signal. The sensor yielding that signal supports a bandwidth of nearly 1 GHz. However, the maximum bandwidth that will be used is going to be around 500Hz to 1 kHz. \$\endgroup\$ – AnatraIlDuck Feb 19 '18 at 9:44
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Firstly you will absolutely need an AOM operating in the VHF region, the common 27MHz sort used for Q switching or in old laser printers will be unlikely to cut it, they have rise and fall times too!

I would finesse this in something like the following way if doing the FPGA thing:

U1 and U2 come into the FPGA digitally, and are converted to a single (or at most a very few) bits of SDM output at maybe 100MHz or so (FPGA digital doings have no issues with that sort of speed), a toy little lowpass network produces an analog signal with a 1MHz or so bandwidth and a swing of about 1V or so for each of U1 and U2, then use two of the LVDS inputs as comparators (They are fast) to do the windowing thing.

An alternative is to feed U1 and U2 to a DAC (Fast DACs are more common then fast ADCs) and then do the windowing thing either with some fast comparators or again with a couple of LVDS inputs to a small FPGA (Means you can do neat things like programmable delays and pulse stretching fairly easily).

On the output, buffer then drive the input to a diode ring mixer or PIN diode switch to control the AOM RF.

The quick way to build this is with comparators and have them switch currents into a diode ring mixer or PIN switching diode, you probably want to be doing physics, not mucking about with logic.

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  • \$\begingroup\$ Thank you for your thorough reply Dan. I will need some time to digest your answer. Concerning AOM: we're going to use an AOM with a rise time of ~150ns, so it is on the edge of the bandwidth \$\endgroup\$ – AnatraIlDuck Feb 19 '18 at 11:30
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I think it's probably difficult to solve this with an ADC as 1MHz is quite fast and you need an internal one as otherwise you already struggle with the speed of the corrsponding interface. What about using an FPGA to process your U_1 and U_2 to SDM signal to drive an analogue comparator for your window?

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  • \$\begingroup\$ Excuse me, what does SDM mean? \$\endgroup\$ – AnatraIlDuck Feb 19 '18 at 7:57
  • \$\begingroup\$ Sigma Delta Modulation, you can use it to set the analogue reference voltage for your comparator while you can set it as a digital input stream. \$\endgroup\$ – po.pe Feb 19 '18 at 8:00
  • \$\begingroup\$ Okay so just so I get it right: you'd suggest converting U_1 and U_2 to a pulse-modulated signal using an FPGA? Wouldn't this also mean you'll need a (digital?) FPGA output with a bandwidth >> 1Mhz? Just as @Jasen says? \$\endgroup\$ – AnatraIlDuck Feb 19 '18 at 9:02
  • \$\begingroup\$ From my understanding your threshold voltages for your comparators namely U_1 and U_2 don't have to change (at least not fast) during operation, or did I get that wrong? And as resolution never was actually designated I assume 8bit would also be sufficient \$\endgroup\$ – po.pe Feb 19 '18 at 9:10
  • \$\begingroup\$ Oh no, sorry for the miscommunication. Neither U_1 nor U_2 are static, they change with 1MHz and both voltages are given with 16 bit. \$\endgroup\$ – AnatraIlDuck Feb 19 '18 at 9:31

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