Using Vivado 2017.4, I am trying to use a clock signal generated by the Clocking Wizard IP. I copied the instantiation and component code block from the Instantiation template, but I am getting some errors related to signal declaration. I have assigned the "count" signal under my architecture header, yet I keep getting an error saying " is not declared".

In addition to "count" I am also getting the same error with my "clk_wiz_0" variable even though I created the component. I also have some syntax warnings that could be contributing to the errors.

I have tried moving the library declarations to after the entity block but that didn't help. I don't think I'm missing any libraries either.

I am new to VHDL so maybe there are some type or syntax issues I am missing? --> signifies a "error <> not declared" error and * indicates syntax warnings. Thanks in advance!

library IEEE;

entity mmcm is
    Port( clk_fpga : in STD_LOGIC;
          reset     : in STD_LOGIC;
          lock_led  : out STD_LOGIC;
          counter_led : out STD_LOGIC);

end mmcm;

architecture Behavioral of mmcm is
    signal clk_10M : std_logic;
    signal count   : std_logic_vector(3 downto 0);

 component clk_wiz_0
     (-- Clock in ports
      -- Clock out ports
      clk_10M          : out    std_logic;
      -- Status and control signals
      reset             : in     std_logic;
      locked            : out    std_logic;
      clk_in1           : in     std_logic
    end component;

   *mmcm_inst : clk_wiz_0*
       port map ( 
      -- Clock out ports  
       clk_10M => clk_10M,
      -- Status and control signals                
       reset => reset,
       locked => locked,
       -- Clock in ports
       clk_in1 => clk_in1


-->ATTRIBUTE BLACK_BOX_PAD_PIN OF clk_wiz_0 : COMPONENT IS "clk_in1, clk_10M, 
reset, locked";

    *process (clk_10M, reset)        --count from 0 to 9 at 10MHz*


   if reset = '1' then
      -->count <= "0000";
   *elseif clk_10M'event and clk_10M = '1' then*
     if count = 9 then
         -->count <= "0000";
         -->count <= count + 1;
     *end if;*
   end if;
end process;

counter_led <= '1' when count = 9 else '0';

end Behavioral;
  • \$\begingroup\$ component clk_wiz_0 is \$\endgroup\$
    – Oldfart
    Commented Feb 19, 2018 at 19:45
  • \$\begingroup\$ @oldfart, the 'is' is optional \$\endgroup\$
    – TonyM
    Commented Feb 19, 2018 at 20:36

1 Answer 1


You need to change 'elseif' to the correct 'elsif'.

Then add a 'begin' above your process, to separate your architecture's declarative region from it's body.

  • \$\begingroup\$ Thank you so much that solved the errors/warnings in my process block! However it is still not recognizing that clk_wiz_0 is declared. Does this need to be created somewhere else in the architecture besides in the component declaration? \$\endgroup\$
    – jjsanders
    Commented Feb 19, 2018 at 23:22
  • \$\begingroup\$ @jjsanders, can you post the precise error message text, as copied from the software tool itself \$\endgroup\$
    – TonyM
    Commented Feb 20, 2018 at 7:05
  • \$\begingroup\$ I actually fixed it. There were just a couple more syntactical errors. Thanks! \$\endgroup\$
    – jjsanders
    Commented Feb 21, 2018 at 16:58

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