# Differential Amplifier's Unusual Behavior

This circuit is made of one differential BJT transistor pair and voltage-amplification stage with negative feedback.

simulate this circuit – Schematic created using CircuitLab

About this circuit for DC conditions. Current through current source equals 2 mA and collector current through each differential transistor pair equals 1 mA. Current into base of VAS (Voltage Amplification Stage) is 20 uA and therefore collector current through it is 10 mA. For loop-gain ratio I firstly decided to be 11 (therefore PF1 was 2,2 kΩ) but then added 100 kΩ potentiometer to it to vary its gain in wide range.

As we speak about small signal analysis or AC conditions if this circuit, things here get a bit more stranger:

1.) Referring to this Bode plot here . The low frequency gain roll-off starts at already 2 kHz! Since I am interested mostly in designing audio amplifier this LF gain roll-off began here to quickly - I was aiming for at least 100 Hz or at 10 Hz of LF gain roll-off if possible. What should I do about it? I did put 100 pF compensation capacitor for improving amplifiers gain bandwidth. (I sampled some values here: (at 100 mVpp input sine) 2 kHz -> Vout = 1 Vpp, 1 kHz -> Vout = 0,88 Vpp, 100 Hz -> Vout = 0,18 Vpp)

2.) Many of you know that, if the closed-loop gain of amplifier is high, that means we have smaller phase margin and greater influence of overshoot/undershoot and ringing at the output (we can see that from square input signal applied to it). And also, if the closed-loop gain of amplifier is low, that means we have larger phase margin (improved stability) and smaller influence of overshoot/undershoot and ringing, but the output signal has longer rise time.

Well, I did some measurements with my scope and function generator. And yes, I did see overshoot/undershoot, ringing, settling time and rise time within output (square) signal, when I was varying the closed-loop gain of amplifier in wide range of values. But there was something strange about it. When the closed-loop gain was high (around 500), I could saw slower rise time of output signal and when closed-loop gain was low (approx. 11), I clearly saw the presence of overshoot/undershoot and ringing within output signal - did I messed up things when I was learning about step response of amplifier or are things that concern overshoot, etc. showing up in reversed order?

3.) I was also trying to find high frequency gain roll-off of amplifier. At high closed-loop gain (around 500), the HF gain roll-off started at around 15 kHz to 20 kHz. But at low closed-loop gain (approx. 11), the HF gain roll-off didn't start at all - in fact the gain was slightly increasing with increasing the input frequency of signal (at 1 MHz it was still increasing!). So the first case seems pretty normal to me, but the second one seems rather extremely unusual than normal. Any ideas what is happening to this circuit at lower closed-loop gains? I thought that amplifier is very stable at low closed-loop gains but obviously not?

• I'm looking at the D.C. conditions. Have you measured the voltage across RE3 to verify your diff pair has 2 mA flowing? – AlmostDone Feb 20 '18 at 20:27
• @AlmostDone Litle bit less - around 1.5 mA; I don't know why exactly but currents are split equally between two collectors of Q1 and Q2. – Keno Feb 20 '18 at 20:54
• I believe Q3 is not fully biased. Calculate the drop you need across RE3 for 2 mA, add ~.6 V to that, and that's what you need between Q3 base and the V supply. – AlmostDone Feb 20 '18 at 21:07
• Edit: ...the -V supply. – AlmostDone Feb 20 '18 at 21:07
• Loop gain is what it is, what you are referring to is the closed loop gain. Please fix. – Andy aka Feb 20 '18 at 21:18

The first thing I noted when I saw your circuit is that the VAS (Voltage Amplification Stage, as you call it) is directly connected to the feedback network and this implies that its gain and its bandwidth are heavily influenced by the value of the equivalent impedance presented by this network: this is the main cause of its "strange" high frequency behavior. There is also another minor slip in the circuit design: I'll show you point by point what is the influences of your design choices on the frequency response of your amplifier, and since I have been somewhat hazy in my former answer, I edited it again, expanding the contents of the last two points

1. The low frequency zero associated to the feedback resistor $$\R_{F2}\$$ and the capacitor $$\C\$$ is too high: calculating the lower cutoff frequency $$\f_{low}\$$ of the feedback network using the component values you chosen, one gets $$f_{low}=\frac{1}{2\pi R_{F2} C}\approx 723\:\mathrm{Hz}$$ However, considering that the BJT $$\Q_2\$$ has probably an input impedance which is at most one order of magnitude greater than $$\R_{F2}\$$, its effect is to push up further $$\f_{low}\$$ therefore the value of 2 kHz you measures seems completely reasonable to me. Solution to this problem: rise the value of $$\C\$$ as much as you can, compatibly with the value of the lower cutoff frequency you want to reach. My advice is to choose $$\C\$$ in order to get $$R_{F2} C=R_b C_{in}$$

2. This is the principal problem caused by the interaction (we could say loading) of your VAS by your feedback network. In other words, when you change the value of the feedback by varying the value of $$\P_{F1}\$$, you change also the open loop gain of the amplifier and thus the gain-bandwidth product $$\GBW\$$ in a way that it is no more a "constant" characterizing the behavior of the circuit. The core of the problem is the behavior of the gain and bandwith of $$\Q_8\$$ when $$\P_{F1}\$$ varies and I'll describe it with the aid of the circuits in following picture: Part a is the VAS electrical schematic (I used a NPN BJT just because it was easier scannerize and edit :D) of the VAS, part b is the equivalent small-signal circuit, part c is the Miller equivalent circuit:

• I assumed $$\C_\mu=C_{bc}+C_c\approx C_c\$$,
• $$\r_\pi=V_T/I_B\approx 1200\Omega\$$ where $$\V_T=k_BT/q\approx 25mV\$$ at $$\T=298\:\mathrm{K}\$$ ($$\25^\circ \mathrm{C}\$$), $$\k_B\$$ is the Boltzmann constant and $$\q\$$ is the elementary charge,
• $$\v_2/v\approx -g_mR_{eq}\$$ is the voltage gain of the stage,
• $$\R_{eq}\$$ is the equivalent resistance which loads the BJT, $$R_{eq}\approx R_c\parallel(P_{F1}+R_{F2})$$
• $$\C_\mu(1-v/v_2)\approx C_\mu\$$ at least as long as $$\v_2/v\geq 10\$$.

The Miller effect causes the presence of a pole at the input and one at the output of the VAS, respectively valued $$p_i=r_\pi\left[C_\pi+C_\mu\left(1-\frac{v_2}{v}\right)\right]\qquad p_o= R_{eq}C_\mu\left(1-\frac{v}{v_2}\right)$$ Changing $$\P_{F1}\$$ changes the value of $$\R_{eq}\$$ and in turn the gain $$\v_2/v\$$ and frequency response of the whole circuit: let's see why.

• When your rise the value of $$\P_{F1}\$$, you get less feedback on the base of $$\Q_2\$$ but far higher gain from $$\Q_8\$$ since $$\R_{eq}\$$ increase. Then $$\p_i\$$ rises by Miller effect, thus the gain rises but the high frequency cutoff decreases stabilizing the circuit: at the unity gain frequency, the phase response of the circuit is practically identical to the one associated to the low frequency pole introduced by $$\p_i\$$, even if the circuit is a second order system.
• On the other hand, if you decrease the value of $$\P_{F1}\$$, you get a higher feedback on the base of $$\Q_2\$$ but far lower gain from $$\Q_8\$$. Then both $$\p_i\$$ and $$\p_o\$$ get smaller and came closer each other in value: the gain is reduced, but the bandwidth and thus the gain-bandwidth product is highly extended (as you noticed in point 3 of your question, there seem to be no high frequency rollback). This make the circuit behave as a second order system. The scope picture you've taken are illuminating in this respect:
1. The first picture on the higher left corner is the step response of you differential amplifier with minimum $$\P_{F1}\$$: it is the classical response of a second order underdamped system, with heavy ringing and over/undershoot.
2. You increase $$\P_{F1}\$$ and the behavior is still the same but both ringing and over/undershoot start to vanish, as shown in the picture on the higher right corner.
3. Continuing the rise of $$\P_{F1}\$$ you reach the critical value of damping: the rise time of the system is optimal, without ringing and over/undershoot, as shown in the lower left corner picture.
4. Finally, the gain rise make the circuit response indistinguishable from the one of a first order system, as shown in the lower right corner picture.

Solution to this problem: if you do not want to design a feedback network with (almost) constant input impedance in order to avoid heavy loading of $$\Q_8\$$ (the heart of the VAS), you should use a (possibly complementary) emitter follower buffer and pick the output signal from the emitter(s) of this stage. This frees your VAS from the heavy dependence on the feedback loop impedance and lets you optimize the circuit gain and response.

3. As explained in the preceding point 2, decreasing the value of $$\P_{F1}\$$ increases the feedback signal on the base of $$\Q_2\$$ and decreases as well the gain $$\v_2/v\$$ of the VAS (referring again to the circuits a), b) and c)): this decrease in gain reduces the Miller effect and improves the bandwidth in such a way that the gain bandwidth product $$\GBW\$$ increases, so the high frequency cutoff is higher than expected, as you noticed.

Final notes. I agree with the suggestion given by jonk: try to cure as more as possible the "elementary" part of circuit design which involves the biasing of your circuit at the chosen quiescent point. It helps your design to satisfy the requirements you ask it in every condition, even under heavy variation of the semiconductor parameters due temperature and production spreads, since this rules out many trivial causes of erratic behavior. Said that, few years ago I made a discrete devices OP AMP involving a similar stages and it worked very well in the bandwidth from 0 to 10 MHz with a gain of ten or slightly more.

• Nice answer! But can you tell me what you think about step response of amplifier as I described in my question? Overshoot/ringing and slow rise time of output signal shows up in reverse order when I vary closed-loop gain. – Keno Feb 21 '18 at 5:01
• I'll improve my answer related to that point later in the evening: however, the behavior is still due to the fact that, while lowering the gain of the circuit, the loading effect of the feedback network rises the gain-bandwidth product so you circuits starts to work in an high frequency region with critical phase margin. – Daniele Tampieri Feb 21 '18 at 6:54
• So, what do you think about that ringing, overshoot and slow rise time of output (square) signal, where those effects showed up in reverse order? – Keno Feb 22 '18 at 4:52
• Keno, I had no time to finish a full update: I added a picture and I'll try to finish later. I'll explain the reverse order of the effects on the rise time: please check it later. Best, – Daniele Tampieri Feb 22 '18 at 6:57
• @Keno Ended update! I hope you'll find the answer clearer and improved. – Daniele Tampieri Feb 23 '18 at 23:03

About this circuit for DC conditions. Current through current source equals 2 mA and collector current through each differential transistor pair equals 1 mA.

Not true.

$R_1$ and $R_2$ form a Thevenin equivalent of:

\begin{align*} V_\text{TH}&= \frac{10\:\text{V}\cdot R_2-10\:\text{V}\cdot R_1}{R_1+R_2}\approx -9.32\:\text{V}\\\\ R_\text{TH}&={R_1\cdot R_2 \over R_1+R_2}\approx 657\:\Omega \end{align*}

You can already see that there is only $680\:\text{mV}$ available for the entire base-emitter voltage of $Q_3$ plus its emitter resistor $R_{E_3}$. If you think you are getting $2\:\text{mA}$ out of that collector, then this means you have only: $$680\:\text{mV}-47\:\Omega\cdot 2\:\text{mA}-657\:\Omega\cdot {2\:\text{mA} \over \beta=200}\approx 580\:\text{mV}$$

for the base-emitter junction. That's not really enough to provide $2\:\text{mA}$ in any BJT I have handy here.

By the way, the sensitivity of your $Q_3$ circuit, derived from the following approach:

$${\text{d}\:I_C \over I_C}\over{\text{d}\:I_\text{SAT}\over I_\text{SAT}}$$

Is about 0.4. Since BJTs vary widely on $I_\text{SAT}$ (factor of 5 or more), this suggests a fairly strong dependence on the BJT you are using at the moment. I'd guess you might see 30-40% variations on collector current just plugging in one BJT vs another one from the same bag of BJTs.

I know you have different questions to answer. But you are starting out with one assumed foundation which is probably incorrect. So this makes the rest of it less interesting.

I do agree with Daniele about the capacitor attached to $R_{F_2}$, though. Certainly, the value is too low.

But it would be good to start with other solid foundations, too.

The low frequency gain roll-off starts at already 2 kHz! Since I am interested mostly in designing audio amplifier this LF gain roll-off began here to quickly - I was aiming for at least 100 Hz or at 10 Hz of LF gain roll-off if possible.

When the impedance of "C" and RF2 are equal, this sets the lower frequency 3 dB gain. I calculate it to be 723 Hz and so at 2 kHz it may just be noticeable. Make C much larger such as 47 uF.

Many of you know that, if the closed-loop gain of amplifier is high, that means we have smaller phase margin and greater influence of overshoot/undershoot and ringing at the output (we can see that from square input signal applied to it). And also, if the closed-loop gain of amplifier is low, that means we have larger phase margin (improved stability) and smaller influence of overshoot/undershoot and ringing, but the output signal has longer rise time.

Here's where you are getting in a muddle. Originally, before you edited your post, your wording about loop-gain was correct - I raised a comment about you calling the closed-loop gain the loop gain in another section that I read and you just did a find and replace globally.

Having said all of that you are still getting into difficulty with these words as orignally written. At the moment, what you have written now is just grade 1 BS so I would urge you to stop theorizing and making a fool of things. Stick to observations and ask questions about those observations.

In short, if you have an amplifier with high loop gain it doesn't matter one bit until you close the loop. If you close the loop with no added components then you get a low closed loop gain. If you close the loop with attenuators you get a higher closed-loop gain and the open-loop gain (with those added attenuators) reduces accordingly.

So, when the closed loop gain is low you are maximizing the throughput of your feedback loop i.e. you are not using added attenuators and this inevitably makes a system potentially more unstable; you are connecting a high gain amplifier's output back to the input and hoping things remain stable and with no attenuation, this is the worst case scenario for potentially creating instability and oscillation.

I thought that amplifier is very stable at low closed-loop gains but obviously not?

No, it is usually closer to (or actually producing) instability.

I did put 100 pF compensation capacitor for improving amplifiers gain bandwidth

The compensation capacitor decreases the amplifier's bandwidth by adding a high frequency roll off (i.e. makes it slower), but is needed to make the amplifier stable.

The low frequency roll off is caused by Cin and C. If you want no low-frequency roll off make the amplifier DC coupled. If you can't do that, increase them until the low frequency roll off is low enough.

Any ideas what is happening to this circuit at lower closed-loop gains? I thought that amplifier is very stable at low closed-loop gains but obviously not?

At lower closed loop gains the amplifier has more bandwidth (same gain * bandwidth product). If the closed loop gain is too low the amplifier will be unstable. The amplifier is unstable if for some frequency the gain from input to inverting input (the open loop gain times the feedback factor) is greater than 1 with a phase greater than 180 degrees. Most general purpose amplifiers are designed to be stable at a gain of 1 (unity gain stable). High speed amplifiers are sometimes not unity gain stable and require a minimum gain of, for example, 10 to become stable.

What we're plotting in the gain margin/phase margin plot is $A_{OL}\beta$ which is the gain from the input to the inverting input. It is not the closed loop gain.

See if we add a divider from the output to the inverting input, e.g. making $\beta = 0.1$, closed loop gain of 10, the phase margin will increase:

I strongly recommend reading Op Amps for Everyone, chapter 5, which gives a good explanation of stability in amplifiers.

• As I decreased the closed-loop gain of an amplifier, it had more bandwidth and therefore larger phase margin; whereas larger phase margin means more stability, right? So, at low closed-loop gains is it stable or not? Because acording to theory, larger phase margin means more stable amplifier. – Keno Feb 21 '18 at 5:10
• @Keno Decreasing the closed loop gain increases bandwidth but reduces phase margin. See my edit. – τεκ Feb 21 '18 at 15:37
• You mean that decreasing closed loop gain increases phase margin? Because your last plot shows that. – Keno Feb 21 '18 at 16:28
• @Keno That plot is not of closed loop gain. It is of open loop gain*feedback factor – τεκ Feb 21 '18 at 17:07
• confusingly this quantity $A\beta$ is often called "loop gain" – τεκ Feb 21 '18 at 17:14