2
\$\begingroup\$

After some primer reading on jtag it looks to be a nifty means to test a FPGA logic design in a consistent and sustainable way.

Let's use altera max 10 as an example. I've read this MAX 10 JTAG Boundary-Scan Testing User Guide. My reading is, to be able to access the user logic the jtag tester (a host pc most likely) will send USER0 or USER1 instructions.

Questions are:

  • How do you implement some logic in the user logic design to catch the commands and parameters, and return some results? Examples?

  • On the host, how do you send those commands, preferably with a low-cost or open-source tool? With some experience, I know Olimex produces some good jtag adapters, and also altera usb blaster is a popular tool. Openocd may be a popular software candidate.

It will be great if somebody can shed lights on any part of the questions.

\$\endgroup\$
1
\$\begingroup\$

Boundary scan (and internal scan) testing, whether using JTAG or not are intended for production test. This is completely different to using JTAG or SWD for software debug. Sometimes the same pins will be used, but this is not a given.

It looks like the Altera USER0, USER1 instructions are used to access internal (user connected) scan chains. This permits you to connect (with a test-mode mux on each flop) all your design flops together into (here two) long scan chains. You have the ability to read and pre-load all of the logic in your design.

Internal scan chains like this can be used to check for manufacturing faults in the actual silicon. If you use scan for the external pins, it gives you a way to test for solder open/short on the PCB.

Scan can be used to debug a design, but it's the last resort. If you experience a lockup which no other debug method can shed any light on the cause, it's possible to use scan to extract the design state just after your failure (before is possible, but that would need a trigger or deterministic failure). This state can be used to guide your investigation into what the design state that causes the failure is, and help reproduce in simulation.

Tools like SignalTap now provide a more user-accessible approach to real-time FPGA debug, these are much more akin to having a logic analyzer hooked in to a pre-defined selection of internal nodes - remember scan is a 1 cycle at-a-time approach.

\$\endgroup\$
0
\$\begingroup\$

After some searching and experimentation a few samples were found online:

  • See the blog talking to the de0 nano using the virtual jtag interface. The author shows in detail how you can design the logic on the FPGA as part of the user logic.

  • Another author of the blog urjtag and python a lightweight hal, also mentioned by the above blog, created some python scripts saved on the google doc server. The python relies on the svn project urjtag. Follow the instructions in the blog, checkout and build urjtag on a linux machine, then download and run the python code shared by the blog author. You'll be able to access the FPGA logic through USB Blaster jtag tool. The author saved his FPGA code to github too. So everything is open sourced!

\$\endgroup\$

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.