Current and Voltage in CMOS Logic Gate

Question

So, in the NAND gate below, I understand how it works with the p-type and n-type transistors. However, my question is what happens with the current when the output is connected to Vdd? If the voltage is high, doesn't that mean current will flow into the output?

Furthermore, if the output is read as high (Vdd), and voltage is supposed to be relative with respect to ground, where is the ground in this circuit when the output is a 1? If the output voltage is Vdd, how does it get read as a high voltage if the output does not have a reference that it can call ground?

Answer 1

Logic levels are voltages with respect to a common reference. We usually call that reference ground, despite the fact it confuses almost every newcomer. As such, whatever is receiving this output also needs to be connected or referenced to the same ground or it wont work.

Shorting the output to Vdd with the output high wont make any difference other than being able to supply more current to whatever the output is connected to.

If you try to pull the output low when it is shorted to Vdd however, one or both of the bottom transistors will blow.

Similarly, if you short the output to ground. With both inputs high nothing much happens. With any inputs low, one or both of the top transistor will release the "magic smoke".