How do you find buried vias in Altium Designer?

Question

I am working on a complex 8-layer PCB to which I have made a number of changes and improvements.

I now want to sent the board out for production and want to check for any unnecessary cost. One of the things I want to check is for any buried vias. The board has plenty of blind vias. If a buried via is found, I want to design it out.

My question is; How do you find buried vias in Altium Designer?

Answer 1

In Altium Designer, have the PCB file open.

1. In the bottom right-hand corner select the PCB menu.
2. Select PCB from the menu.

The PCB tab opens and by default docks to the left-hand side.

3. Open the dropdown menu.
4. Select Hole Size Editor.

5. Find an entry that doesn't connect to either the Top Layer or Bottom Layer and select the check box.

The burried vias will show up in the areas highlighted above, if any.

Answer 2

There are several easy ways to do this:

1. Never make vias between the "wrong" layers to begin with. In the layer stack manager, drill pairs dialog, you have to define each pair of layers you want to enable placing vias to connect:

If you never enable placing vias between layer 4 and 6 (for example), Altium simply won't let you place vias between those layers, so you know that no such vias exist in your design.

2. First, generate your manufacturing outputs once. Then just look at the drill table in your fab drawing. You did make a fab drawing didn't you? If you are making a design complex enough to have blind vias, you absolutely should be providing your vendor with a fab drawing:

If you somehow accidentally made a via between layers you shouldn't have, you'll easily see this via listed on its own line in the drill table.

3. Visual check. Any blind or buried vias will be displayed with their center split into to colors to indicate the layers they connect:

4. Design rule check. If you set your design rules to disallow blind and buried vias and run DRC, any remaining blind or buried vias from previous editing should be found as DRC errors (I have not tested this).