In my FPGA design, I have some input signals that need to be delayed considerably before they reach the first clocked register. There are delay elements near the pins for exactly that purpose, but their maximal delay is still too low.
So I want to force the signals on a detour through the FPGA in order to achieve the required delay. I realize this is not "by the book", but maybe others have been in the same situation.
Question: Are there some "best practice" rules for this kind of thing?
Provided that the required delay can be achieved "on paper" in both ways, which is to be preferred: signals travelling great distances or signals going through combinatorial logic? What kind of logic is best suited for that purpose (LUT, carry chain,...)?
If you're an experienced designer and can't think of any difference, that too would be useful information.
I'm using an Altera Cyclone V, but the question should be answerable in general.